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some questions about DDR3 timeings on my cunstom 8148 board

shawnstone
Intellectual 850 points

hi,

    Our custom board PCB about DDR3 layout is 

　 　 Byte 0 Byte 1 Byte 2 Byte 3
DDR0 CK trace 2.6 2.6 3.6 3.6
DQS trace 1.4 1.63 1.07 0.92
DDR1 CK trace 2.56 2.56 3.56 3.56
DQS trace 1.62 1.17 1.26 0.98

wether the  Parameters are within the allowable range or not ,We use simulation of CCS to get WR DQS,RD DQS,RD DQS GATE,WR DATA ,

 we make ubootall,But, when we load the uboot .min.nand  and uboot.bin  to my custom board  , and power up the board ,but  uart has not any information.

Could you help me?

Thanks in advances.

Best  Regards,

stone

  • 0
    TI__Genius 13460 points
    Hi,
    Have you filled in the excel attached and modify the DDR timing parameters in uboot ?
  • 0 in reply to Eason Wang
    TI__Genius 13460 points

    For details , please refer 

    Basically, you need to change the timing paramters, and do the DDR SW leveling.

    The excel I mentioned is 

    you need to check the datasheet of DDR and filling the excel to get the DDR register value which need to be filled in uboot source code.

    BR,

    Eason

  • 0
    TI__Guru**** 170625 points
    You can also try to boot your board with low DDR3 frequency. If you can boot with low DDR3 frequency then you should update your DDR3 timing settings to be able to boot with high DDR3 frequency (max is 533MHz).

    processors.wiki.ti.com/.../Debug_Tips_for_DM81xx_Boot_Fail
    processors.wiki.ti.com/.../DM814x_Hardware_Design_Guide

    Can you try with UART boot. In UART boot, the 1st stage bootloader (u-boot.min.uart) loads and run from OCMC RAM (no DDR3 involved).

    Can you also run the DM814x/AM387x HW diagnostic test CCS_Code_BB/src/CCS_Test_code/Base_Board/DDR3

    This CCS test application validates the DDR memory for its ability to perform write access; read access and data storing ability. The test application writes a known pattern into the entire memory and then reads back the same. The known pattern written into the memory is the incremental hexadecimal numbers. After writing to the entire memory area, this application reads them back and validates the data read. If the data read does not match the expected pattern, this test is declared failed. It is declared pass otherwise.

    BR
    Pavel
  • 0 in reply to Eason Wang
    Intellectual 850 points
    Hi,
    we have finished the simulation by CCS, and refresh the timing paramter to uboot.
    1、 DDR on 400M , we get the timing paramters and do the DDR SW leveling simulated by CCS. after refresh the paramter to uboot, uboot and kernel is loaded successlly .
    2、 DDR on 533M, we alseo get the timing paramters and do the DDR SW leveling simulated by CCS. after refresh the paramter to uboot, However, uboot cann't be loaded, all is failed !

    what is wrong with it ? and Whether we need to adjus the core voltage?

    Best Regard,
    Stone
  • 0 in reply to Pavel Botev
    Intellectual 850 points
    Hi,
    we have finished the simulation by CCS, and refresh the timing paramter to uboot.
    DDR on 400M , we get the timing paramters and do the DDR SW leveling simulated by CCS. after refresh the paramter to uboot, uboot and kernel is loaded successlly . However, on 533M DDR ,we use the same way to get the new timing paramters and do the DDR SW leveling simulated by CCS,but uboot cann't be loaded.

    what is wrong with it ? and Whether we need to adjus the core voltage? How we can adjus the core voltage?

    Best Regard,
    Stone
  • 0 in reply to shawnstone
    TI__Guru**** 170625 points

    Stone,

    shawnstone said:
    However, on 533M DDR ,we use the same way to get the new timing paramters and do the DDR SW leveling simulated by CCS,but uboot cann't be loaded.

    what is wrong with it ? and Whether we need to adjus the core voltage? How we can adjus the core voltage?

    The core voltage change (1.1V to 1.35V) should be done in u-boot, you can not do it before u-boot. The u-boot should be loaded fine with DDR3 533MHz at 1.1V. Then if you do not switch to higher voltage (1.35V) the linux kernel will be not able to boot. See the below e2e thread for more info:

    BR
    Pavel

  • 0 in reply to Pavel Botev
    Intellectual 850 points
    Hi,
    yeah, thanks for your help! we had solve the problem! we should ajust the core voltage to 1.35V, every thing is well!

    Thank you!

    Best Regard,
    Stone