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DRA7xx DSP core : How to change frequency of DSP CORE ?

Naveen Shetti
Intellectual 690 points

Hello,

We are working on dra7xx-evm(OMAP5777)  board with following setup :

1.  linux-3.12 kernel

2. Toolchain- gcc-linaro-arm-linux-gnueabihf-4.7-2013.03-20130313_linux.

3. Filesystem- arago-glsdk-multimedia-image-dra7xx-evm.

4. glsdk_6.10.00.02

5. ipc_3_23_00_01

6. bios_6_37_03_30

7. xdctools_3_25_06_96

8. CCS5.5

We tried to identify the DSP clock frequency by profiling task_sleep(1000) i.e. task sleep of 1 sec. It evaluated to 575 mega cycles. With this we presume that the DSP core is running at 575MHz. is this understanding correct ? Also, we need to change this frequency to 700MHz ( this is the max DSP freq that can be supported on this EVM as per the datasheet).

Please let us know how this can be done.

We tried to change CPU freq in the .cfg file as mentioned in the forum http://e2e.ti.com/support/embedded/tirtos/f/355/t/277692.

  • 0
    TI__Mastermind 21645 points
    Hi Naveen,

    As mentioned in the post whose link you shared, SYS/BIOS does not configure the PLLs. The expectation is that the bootloader or the boot master (A15 core) will configure the PLL to run at a given frequency and the BIOS.cpuFreq config param is set to the this value at build time.

    Typically in a CCS debug environment, we use gel files to configure the DSP PLL but since you are running Linux on the A15, you can configure the PLL from Linux before loading the application to the DSP.

    You can look at the CCS gel file that is used to configure the DSP PLL for reference code. This gel file comes with the chip support package for DRA7xx which it looks like you already have installed. Here's where you would find it:
    C:\ti\ccsv5\ccs_base\emulation\gel\DRA7xx\DRA7xx_prcm_config.gel (Look for dpll_dsp_config() function in this file)

    Hope this helps.

    Best,
    Ashish