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Booting DSP C6674 in ASMP mode (Booting of all 4 cores)

ti_user
Expert 1265 points

Hi Sir,

My Custom uses a TI DSP C6674 and currently enabled to boot :

  • IBL from I2C EEPROM
  • SYS/BIOS Application from NAND Flash

My Application uses only one DSP core right now.

Now I have to work with all cores, they have to be booted automatically and should be ready to run.

Can you please guide me how to approach this and make this happen.

Awaiting for your response.

Thanks,

Mani Kumar

  • 0
    TI__Guru* 81335 points
    Hi Mani,
    I recommend you to refer Multicore Application Deployment (MAD) for running the applications on all core. The MAD demo is available in MCSDK installation directory.

    Please refer below MAD wiki for more information.
    processors.wiki.ti.com/.../MAD_Utils_User_Guide

    Thank you.
  • 0
    TI__Guru** 116830 points
    Hi Mani,

    Other than the MAD utilities recommended by Raja, I would also request you to take a look at the multi-core boot example given in MCSDK under the directory path mcsdk_2_01_02_06\tools\boot_loader\examples\srio\srioboot_helloworld/src. This example shows how you can wake up secondary cores using IPC interrupts and populate the magic address for the cores to start executing code. This structure is useful, if you want to create a single application that boots on all cores and then has control code to parititon itself across secondary cores by checking the core number on which is running.

    Regards,
    Rahul
  • 0 in reply to Rahul Prabhu
    Expert 1265 points

    Hi &


    Thanks alot for your inputs.

    Initially i planned to work with MAD Utils, as I have a query about using Method 2 by referring srio example - How can other cores gets initialized and also how that core can be loaded with image.


    While trying MAD Utils, I was able to build successfully with example project given (app1 & app2). But, while I'm trying with my actual application i followed the below steps :

    - Build my SYS/BIOS or RTSC Project with : dynamic & relocate option enable in compilation options

    - Replaced and Renamed in default example directory as myappname.out to app_1.exe and app_2.exe

    - Modified the "deployment_template_C6678.json" at "map-tool\config-files" directory as attached file.

    But when the phyton mapload.py is running the below error is coming :

    ERROR: xipAssignAddrToSegments() - segment: 12 in app: app1  cannot be made XIP
    ERROR: assignAddrToSegments Failed in Partiton: ddr-code

     
    Can some one Help.  Attached : .json file and my out file (Hope the8053.files.zip attached files  are viewable!)
    Thanks

    Mani Kumar

  • 0 in reply to ti_user
    TI__Guru** 116830 points

    Mani,

    In Method 2, the bootROM will initialize the SOC and load a single image into memory. All cores will run the same image but the code will have control code to check which core is running the image and partition the code. Core0 boots first so it will need to populate the entry point of the image in the magic address for all the secondary cores and issue them an IPC interrupt to wake them up.

    Regards,
    Rahul

    PS: YOur error indicates that some code segment that you have defined in your linker command file can`t be placed in the ddr-code section as defined in the python script. I will look at your files and let you know if I see anything that might cause this issue.

    IF you are using section definition that are not defined in the maptool.py script then you need to add those sections so that the tool can place it correctly in either ddr-code ot ddr-data section. Please look at the following post for debugging this issue:

  • 0 in reply to Rahul Prabhu
    Expert 1265 points

    Hi Rahul,

    Thanks for your information about Method 2 and understood it well with explanation.


    I will be waiting for your inputs about generating MAD ROMFS image using my .out files.

    Thanks,

    Mani Kumar

  • 0 in reply to ti_user
    Expert 1265 points
    Hi,

    Now I'm able to build and Run my code using "MAD Utils - Pre-Linker bypass mode", each gives a print with its core id and i could able to see on my UART.

    As mentioned in link : processors.wiki.ti.com/.../MAD_Utils_User_Guide,
    section : "Loading and running MAD linked image using CCS"

    I'm able to execute output C6678.bin file using CCS Tool Successfully.

    But, I have a query of how to find which core is executing from what memory address and will it share all Global variable space, Stack and Heap between all cores or it is individual to each core? If its independent how to find those addresses.

    Thanks
    Mani Kumar