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GPMC and CLKOUT2

eugenio
Expert 1505 points
Other Parts Discussed in Thread: AM3359

Hi all.

I'm interfacing a CycloneIV FPGA with AM3359 Sitara CPU via GPMC memory controller configured to perform asynchronous transfers.

To overcome some of the oddities in crossing clock domains, FPGA has only one 100MHz clock, coming straight from CLKOUT2.

CLKOUT2 is configured to share the same source and divisor factor of L3_Slow clock, that feeds GPMC controller:

Reading TRM I understand that GPMC changes control signals on rising edges; CLKOUT2 and GPMC FCLK are in phase signals (same source, same division factor), so I can use CLKOUT2 as synchronous source clock for the interface:

But, with an oscilloscope I see that GPMC changes data on falling edges:

Is TRM wrong? Am I wrong?

  • 0
    TI__Guru**** 393215 points

    Hi Eugenio,

    Please read section 6.2.4 of the AM335X Datasheet Rev. G.

  • 0 in reply to Biser Gatchev-XID
    Expert 1505 points
    Hi Biser, thank you for your quick reply.

    I've read the datasheet before trying the CLKOUT2 trick. The warning is about unpredictable jitter, because CLKOUT2 clock is sourced from any configuration of internal plls and divisors. Some of these pll are "low jitter" ones, others are without jitter specification. Is this correct?
    Nevertheless "jitter" sounds to me as something that's like "wobbling around".
    In this case CLKOUT2=L3F/2 is permanently 180° shifted with respect to L3S clock. No way to figure out why...

    Will this phase inversion be always the same? May I rely on this?
    If not, how can I synchronize my entire FPGA design to GPMC clock?
  • 0 in reply to eugenio
    TI__Guru**** 393215 points

    The note in this section specifically says: "...and CLKOUT2 clock outputs should not be used as a synchronous clock for any of the peripheral interfaces because they were not timing closed to any other signals." This means that their timing is indeterminate to any other peripheral signal timing.

    As for the GPMC_CLK, this isn't a continuous clock, it only runs during synchronous GPMC transactions.