How much is the current of VDD1V5 in TMS320C6672 ?

Balder zhang

Prodigy 90 points

Other Parts Discussed in Thread: TMS320C6672, TMS320C6678

HI,

I want to know How much is the current of VDD1V5 in TMS320C6672 .

I did not use the DDR3 SDRAM ,but the current of VDD1V5 Jump among 0.1A 、0.8A and 1.5A.

What will cause this situation? Power sequence or other things?

over 10 years ago

0 Senthilkumar Srinivasan over 10 years ago

TI__Mastermind 43660 points

Hello Balder,

Welcome to the TI E2E forum. I hope you will find many good answers here and in the TI.com documents and in the TI Wiki Pages (for processor issues). Be sure to search those for helpful information and to browse for the questions others may have asked on similar topics (e2e.ti.com).

There is a power consumption model available for C6672 in the device product folder. I believe it could help you to find out the current consumption of VDD1V5 rail.

www.ti.com/.../toolssoftware

Regards,
Senthil

0 Balder zhang over 10 years ago in reply to Senthilkumar Srinivasan

Prodigy 90 points

Hi Senthil,
From the "C6672_Power_Consumption_Summary", I know the maxim current is about 0.3A .
I did not use the DDR3 SDRAM ,but the current of VDD1V5 Jump among 0.1A 、0.8A and 1.5A.
What may cause the abnormal situation? Power sequence or other things?

0 Tom Johnson 16214 over 10 years ago in reply to Balder zhang

TI__Mastermind 46460 points

Balder,

You report that you did not use DDR3. This is an unusual design. Did you follow all of the recommendations for unused DDR pins in the Hardware Design Guide for KeyStone I Devices SPRABI2C? Please list the connections for all DDR3 related pins so we can cross-check. Include signals link AVDDA2, VREFSSTL, PTV15, DDRCLKP/N as well as the obvious DDR3 pins.

How are you measuring the DVDD15 supply current? When you report it at different levels, is this on different boards or the same board after different power cycles or does it vary continuously on a single board while powered. Do you see this same behavior on multiple boards?

Tom

0 Bill Taboada over 10 years ago in reply to Balder zhang

TI__Mastermind 42545 points

Hi Balder,
We've had one report of this previously. We found that the DDRCLK needs to be present even for boards that do not have a DDR3 interface. Without the clock, the interface is not reset correctly and will sometimes enter a state which draws more current from the DVDD15 supply. You will need to connect a clock to the DDRCLK intputs to fix the problem. This will be updated in the next release of the Hardware Design Guide.
Regards,
Bill

0 Tom Johnson 16214 over 10 years ago in reply to Tom Johnson 16214

TI__Mastermind 46460 points

Balder,

Please see https://e2e.ti.com/support/dsp/c6000_multi-core_dsps/int-c66x_multi-core_dsps/f/513/p/342646/1198753#1198753. This device has the same architecture. Please verify that adding a clock to DDRCLKP/N during reset resolves the problem. A litbug has been posted to correct this in the HWDG.

Tom

0 Balder zhang over 10 years ago in reply to Bill Taboada

Prodigy 90 points

Hi Bill,
Thank you for your reply!
Is there the same problem on TMS320C6678? And does it work if I extend the reset time?

0 Balder zhang over 10 years ago in reply to Tom Johnson 16214

Prodigy 90 points

Hi Tom,
Thanks for your reply!
But i can not see e2e.ti.com/.../1198753.
Can you email the HWDG to me ? My email is njy7270@126.com.

Does this bug appear on TMS320C6678? If the answer is "NO", I will replace TMS320C6672 with TMS320C6678 in my application !

Regards,
Balder

0 Balder zhang over 10 years ago in reply to Bill Taboada

Prodigy 90 points

Hi Bill,
Another question,
Does it work if I disable the ddr interface? And how can I disable the ddr interface by update the register?

Regards,
Balder

0 Senthilkumar Srinivasan over 10 years ago in reply to Balder zhang

TI__Mastermind 43660 points

Hello Balder,

The thread that Tom has mentioned in his post is an internal thread you cannot view that as a community member.

You can find the latest HWDG in the below link. Please note this is not updated for DDR3 clock requirement when DDR3 is not used.

http://www.ti.com/lit/an/sprabi2c/sprabi2c.pdf

The C6672 and C6678 are from the same family and DDR3 clock requirement when DDR3 is not used is applicable for both the devices.

Regards,

Senthil

0 Bill Taboada over 10 years ago in reply to Balder zhang

TI__Mastermind 42545 points

Hi Balder,
Unfortunately, disabling the DDR interface doesn't remove the need for a clock. Without a clock the DDR won't place the interface into the disabled state correctly.
Regards,
Bill

0 Balder zhang over 10 years ago in reply to Bill Taboada

Prodigy 90 points

Hi Bill,

There is a LVCOMS CLOCK on my board, can I connect this clk to the LJCB ddr clk?
Is there any reference on this usage?

Regards,
Balder

0 Balder zhang over 10 years ago in reply to Balder zhang

Prodigy 90 points

Sorry! Not LVCOMS CLOCK. That is HCMOS as below:
Output waveform HCMOS
Output voltage level low (VoL) ---> 0.1 max
Output voltage level high (VoH) ---> 0.9 min
Can I connect this clk to the LJCB ddr clk P directly , and connect the LJCB ddr clk N to GND ?

0 Tom Johnson 16214 over 10 years ago in reply to Balder zhang

TI__Mastermind 46460 points

Balder,

The clock input buffers are LJCB. They are directly compatible with LVDS signal levels. The single-ended clock that you mentioned is not directly compatible. It can be used with proper level shifting and biasing. Please refer to the KeyStone Clocking Guide SPRABI4. Example circuits are shown for LVCMOS to LVDS in section 4.2.5. Your levels are different so the resistor values will need to be adjusted. You should be able to make this work. Please make sure that your HCMOS clock is fast enough. The minimum frequency for the DDRCLK input is 50MHz.

Tom

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How much is the current of VDD1V5 in TMS320C6672 ?