SDRAM Problem

Hello Ganesh, 

In addition to Titu's comment.

You can apply SDRAM timing values in the u-boot, and try to run this new configuration on your board.

 Take a look on the file u-boot/arch/arm/cpu/armv7/omap5/sdram.c: and apply your SDRAM configuration:

* For any new board with different memory devices over-ride one or more
* of the following functions as per the CONFIG flags you intend to enable:
* - emif_get_reg_dump()
* - emif_get_dmm_regs()
* - emif_get_device_details()
* - emif_get_device_timings()
*/

.....

/*
* DRA752 EVM board has 1.5 GB of memory
* EMIF1 --> 2Gb * 2 = 512MB
* EMIF2 --> 2Gb * 4 = 1GB
* so mapping 1GB interleaved and 512MB non-interleaved
*/

You must also check your board configuration in another two files:

u-boot/arch/arm/cpu/armv7/omap5/hw_data.c

static const struct dpll_params

const struct ctrl_ioregs ioregs_dra7xx_es1

void __weak hw_data_init(void)

struct dplls dra7xx_dplls = {
.mpu = mpu_dpll_params_1ghz,
.core = core_dpll_params_2128mhz_dra7xx,
.per = per_dpll_params_768mhz_dra7xx,
.abe = abe_dpll_params_sysclk2_361267khz,
.iva = iva_dpll_params_2330mhz_dra7xx,
.usb = usb_dpll_params_1920mhz,
.ddr = ddr_dpll_params_2128mhz,
.gmac = gmac_dpll_params_2000mhz,
};

struct dplls dra72x_dplls = {
.mpu = mpu_dpll_params_1ghz,
.core = core_dpll_params_2128mhz_dra7xx,
.per = per_dpll_params_768mhz_dra7xx,
.abe = abe_dpll_params_sysclk2_361267khz,
.iva = iva_dpll_params_2330mhz_dra7xx,
.usb = usb_dpll_params_1920mhz,
.ddr = ddr_dpll_params_2664mhz,
.gmac = gmac_dpll_params_2000mhz,
};

u-boot/arch/arm/cpu/armv7/omap5/hwinit.c

/* DDR3 specific IO settings */
static void io_settings_ddr3(void)

Could you specify your DDR memory devices connected to DRA7xx?

Best regards,

Yanko

Hi Yanko,

I have verified lisa_map_2G_x_1_x_2,  lisa_map_2G_x_2_x_2 in u-boot code, those values are same as you specified. Actually we are using DDR same as DRA752 EVM only. Only change is there data bus is randomly connected to data lines, we have connected data bus in an order, but that should not cause any problems.

I was able to connect JTAG and debug, but i guess the values that i am getting in the registers is what we have written in gel files. By doing like that how can you ensure the DDR timings?

Thanks & Regards,
Ganesh

Hello Ganesh,

I was able to connect JTAG and debug, but i guess the values that i am getting in the registers is what we have written in gel files.

- Yes, you can test your DDR by this way. In addition you can use values from gel files as apply them in u-boot.  

By doing like that how can you ensure the DDR timings?

For calculating DDR timings you must use VAYU EMIF4D5E DDR3 EMIF2 Programming.xls spreadsheet. You can obtain this document from your FAE.

Best regards,

Yanko