Memory map for TMS320TCI6614 cortex A8

Yes, please refer to the datasheet already mentioned for the device memory map.  There is DDR and MSMC (faster access) available to all cores.  Have you considered using the Queue Manager? The QMSS (Multicore Navigator) provides a global hardware queuing system that is appropriate for certain linked lists.  Please search for SPRUGR9H on ti.com for the document.

Hi

The QMSS can not be used because of some reasons. I made the queue to store packets coming in from Ethernet port and and want the DSP to get the address of the first node so that it could get the data and use it for further processing. How can I get the memory location of my 1st node and pass it to DSP.  I understand that ARM is not allowing me to write data to a particular address. 

Thanks 

Raunak

The ARMs have access to all global addresses, including DDR, and MSMC.  There are many ways to accomplish passing an address from the ARM to DSP. Knowing the best one to recommend for your situation is something I can't do without a lot more information.  Here are a few options:

1) Create your own mailbox using a global (uncached) location(s) and a semaphore, interrupt, or global memory handshake.

2) Simply push a descriptor to the QM from the ARM and have the DSP pop it from the queue.

If the reason for pushing the address to the DSP is to provide a location for data to be processed by the DSP, it may be more efficient to have the ARM push it directly to the QMSS packetDMA, and let the DMA place it automatically in the local L2 memory of the DSP.

  -dave