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Which clock chip for C6678 clock tree?

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Other Parts Discussed in Thread: CDCM6208, CDCM6208V1

In the Hardware Design Guide for Keystone II Devices, we recommend the CDCM6208. But this device comes in two versions for different PLL operating frequencies:


CDCM6208V1 - 2.39GHz to 2.55GHz
CDCM6208V2 - 2.94GHz to 3.13GHz

Which one should the customers choose, or what are the normal settings for this device?

Since it is the one recommended in the HDG, I assume TI has that information, please?

Regards,
RandyP

  • Hello Randy,

    I believe, we can use either of the device. However the loop filter components and the pre-configured settings will be different for each of the devices.

    I will check with internal team on the recommended settings for both the devices and update you.

    Regards,
    Senthil
  • Hi Randy,

    The answer depends on a number of factors. Each of the CDCM6208 versions has a different VCO frequency but both use programmable prescalers after the VCO to feed the output dividers. These prescalers can be divide by four, five or six. The choose of the version of the CDCM6208 depends on the VCO frequency that prescales to the most useful intermediate frequencies needed for the customer designs. The K2H EVM used the CDCM6208V2 because it could generate a valid VCO frequency from the 19.2MHz input clock to get both the 122.8MHz frequency and the 312.5MHz/156.25MHz/100MHz/125MHz frequencies. The K2E EVM used a 25MHz input clock therefore the VCO frequency of the CDCM6208V2 was a better fit for generating 312.5MHz/156.25MHz/100MHz frequencies needed. Note that we attempted to use integer dividers for the output dividers of the CDCM6208. Integer dividers provided a clock with less jitter. More information on the Edison clock design can be found in the clock generator TI Design.

    The XML files used by the CDCM6208s for each of the EVMs can be found on the manufacturers webpage.

    Regards,

    Bill