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TMS320c66X DSP CorePac User Guide misundertanding

Peter010
Genius 4165 points

Hello everyone

In the TMS320c66X DSP CorePac User Guide, it says that:"L1P memory cannot be cached within Level 1 data (L1D) cache, Level 1 program (L1P) cache, or Level 2 (L2) cache within the same C66x CorePac." I know every words of this sentence. I know what is L1P, L1D, and L2, but I do not know what this sentence what to tell me. What does the "L1P memeory" mean in that sentence?

Another question, in the section 3.3.6.1 L2 to L1D Cache Coherence Protocol, it says that:"Snoop-read is sent to L1D when L2 detects that the L1D cache holds the requested line, and that the line is dirty. L1D responds by returning the requested data." What does the "holds the requested line" mean? Does this sentence mean that when core is going to read a dirty line in L1D cache and previously this line is modified by the IDMA/DMA in L2, L2 would send this new data to L1D cache automatically? 

Thanks.

Xining Yu

  • 0
    TI__Mastermind 43660 points

    Hello Xining,

    In the TMS320c66X DSP CorePac User Guide, it says that:"L1P memory cannot be cached within Level 1 data (L1D) cache, Level 1 program (L1P) cache, or Level 2 (L2) cache within the same C66x CorePac." I know every words of this sentence. I know what is L1P, L1D, and L2, but I do not know what this sentence what to tell me. What does the "L1P memeory" mean in that sentence?

    The above statement mentions that the content of the L1 program memory cannot be cached on the same C66x CorePac cache memory. You can only cache the contents in to the other CorePac cache memory on the same device.

    Another question, in the section 3.3.6.1 L2 to L1D Cache Coherence Protocol, it says that:"Snoop-read is sent to L1D when L2 detects that the L1D cache holds the requested line, and that the line is dirty. L1D responds by returning the requested data." What does the "holds the requested line" mean? Does this sentence mean that when core is going to read a dirty line in L1D cache and previously this line is modified by the IDMA/DMA in L2, L2 would send this new data to L1D cache automatically? 

    Please refer the below thread where you could find detailed explanation on this.

    https://e2e.ti.com/support/dsp/c6000_multi-core_dsps/f/639/t/410770

    Regards,
    Senthil

  • 0 in reply to Senthilkumar Srinivasan
    Genius 4165 points

    Thanks for replying, Senthil.

    For my second question, I still have some confusing. Can you tell me what the " holds the requested line" means in the question 2?

    Another question, It says that:"Simultaneous DSP and DMA/IDMA accesses to distinct L1D memory banks do not stall." Does it mean that for simultaneous visiting different L1D memory on distinct C66x CorePac there will be no stall?

    Xining

  • 0 in reply to Peter010
    TI__Mastermind 43660 points

    Hello Xining,

    For my second question, I still have some confusing. Can you tell me what the " holds the requested line" means in the question 2?

    Snooping is a process where the individual caches monitor address lines for accesses to memory locations that they have cached. Here the L2 send the snoop read (SNPR) command when it detects the L1D holds the requested address line and L1D returns the requested data from that particular address.

    Another question, It says that:"Simultaneous DSP and DMA/IDMA accesses to distinct L1D memory banks do not stall." Does it mean that for simultaneous visiting different L1D memory on distinct C66x CorePac there will be no stall?

    Yes, your understanding is correct.

    Regards,

    Senthil