Hello, all
If I try to use only L2 layer functions in CPSW+PA, is any software job needed for packet switching for all ports(port0 ~ port4)?
Please explain how to work CPSW+PA for features as follows.
1. VLAN
1) How to be packets handled at VLAN Unaware Mode?
a. received packets with VLAN Tagged
b. received packets with VLAN Untagged
2) How to be packets handled at VLAN Aware Mode?
a. rececived packet with VLAN Tagged (included member VLAN)
b. rececived packet with VLAN Tagged (not included member VLAN)
c. rececived packet with VLAN Untagged
2. Mac Address Table
1) Is automatic learning & automatic aging out supported (including host port)?
2) Is static mac address configuration supported (including host port) ?
3) Number of total mac address table entry(per device, per port)
- Does ALE(Address Lookup Engine) table mean "mac address table" ?
- As for document, the number of ALE entries is 1024
Is this entries used for both mac address table and vlan table (shared) ?
4) when mac address table enties are full, how is new mac address handled ?
3. Packet Buffer
1) total packet buffer size
2) Is shared buffer mode supported ? (between ports, between queue)
4. Statictics
1) Is simulaneous statistics monitoring for total 5 ports supported (independently per port) ?
(as for document, statistics register STATSB seems to be only for Port 1 (and,or) 2
STATSD seems to be only for Port 3 (and,or) 4
STATSA seems to be for Port0 (destined to port1,2)
STATSC seems to be for Port0 (destined to port3,4)
and it seems not to be supported for simultaneous statistics collecting for port 1 and 2 / port 3 and 4 seperately)
5. QoS releated
1) Supported Scheduling Mode (SPQ/WRR/DWRR ...)
2) Mode of mapping packet to queue
- DSCP(TOS) to Queue ?
- 802.1p CoS to Queue ?
3) Rate Limit / Storm Control
- RX Port Ingress Rate Limit (by PPS or kbps)
- TX Port Egress Shaping (by tocken bucket, by PPS or kbps)
- Storm Control for following packets
. Broadcast / Multicast / DLF(destination lookup failture)
6. Host Port (Port0) Feature
- Is sending packet to host port with vlan tagged supported ?
- How could host cpu recognize received port of packet ?
- When host cpu sends packet via host port to switch, how egress port determined ?
(Is any software intervention needed ? or is determined by only switch hardware ?)
7. ETC
1) Port Mirroring Support (and any limitation if exist)
2) Port Trunking(Link Aggregation) Support (and any limitation if exist)
3) PCL(Policy Control List) Support (and any limitation if exist)
4) Switch Register Access interface (is MDIO only for PHY device?)
5) Usage of some registers of switch: MAC1_SA_LO, MAC1_SA_HI ~ MAC4_SA_LO, MAC4_SA_HI
Thank you.
