Timestamp is not right when rach preamble receives.

zhou zhou

Intellectual 280 points

Hi,

Some question needs your help, about the timestamp of the receiving preamble.

test environment:

chip: Keystone,TCI6618

RACCM_RACFL_VERSION_ID (0x0200000C)

RACCM_RACFL_VERSION_STR "RACFL Version: 02.00.00.35.PATCH.06"

When RAC receives the preamble and generates the OD, the gap between the the access slot ID (from OD) and the RAC time is 7 slots, normally it shall be 3 slots. Thus will cause the AICH timing to be wrong and UE can not receive the ACK from BTS.

rachMeasOffset= -12806 chips.

It will be reproduced with reset the system.

Thanks,

Zhou Guobiao

over 9 years ago

0 Raja over 9 years ago

TI__Guru* 81335 points

Welcome to the TI E2E forum. I hope you will find many good answers here and in the TI.com documents and in the TI Wiki Pages (for processor issues). Be sure to search those for helpful information and to browse for the questions others may have asked on similar topics (e2e.ti.com). Please read all the links below my signature.

We will get back to you on the above query shortly. Thank you for your patience.

0 Raja over 9 years ago in reply to Raja

TI__Guru* 81335 points

As the RAC is not supported in public forum this has been closed through private discussions.

Thank you.

0 zhou zhou over 9 years ago in reply to Raja

Intellectual 280 points

hi,

I have moved it to the private forum with the same title, but no one updated the question.

Could you help to push it? It seems too slowly.

thanks,

Zhou Guobiao

Processors

Processors forum

Timestamp is not right when rach preamble receives.