C674x VTP IO Calibration Power-Down Timing

Hi,

We are looking into your request and will get back to you soon.

Thanks & regards,
Sivaraj K

Dear Tsutomu,
I think, no, you can't use that bit in user program, VTPIO_CTL register can be used while powering up reset of mDDR/DD2 module and always you should follow the sequence mentioned in 15.2.13.1 of OMAPL138 TRM.

If customer need any power savings then use DDR self refresh mode, refer chapter "Power Management"
Also refer to the following TI wiki page.

processors.wiki.ti.com/.../Power_Module_for_C6748_and_OMAP-L138
processors.wiki.ti.com/.../42_Power_Consumption_Summary

Titus,

Thank you for your reply.
I understand that the POWERDN bit of the VTPIO_CTL register should be set by a user program because the ROM bootloader doesn't perform this step.

https://e2e.ti.com/support/dsp/omap_applications_processors/f/42/p/135592/491974#491974

https://e2e.ti.com/support/dsp/tms320c6000_high_performance_dsps/f/115/t/459081

But we still should set the bit by the secondary user bootloader in the internal RAM before we load an application program into DDR2, right?

Best regards,
Tsutomu Furuse

Titus,

Thank you very much for the answer.

Why the customer is setting that bit ?
for power save ??

He would like to set the POWERDN bit for power save although I don't know how big the reduction is. And I'm not sure if leaving the VTP controller on is safe for the DDR2 operation.

And why they need to set while bootloader stage if they want to do ?

He is thinking about immediate user application loading from the UART AIS boot without the secondary user bootloader running on the internal RAM. Because the ROM bootloader doesn't perform the POWERDN setting as I decribed in my last post, he doesn't have a timing to perform it.

Best regards,
Tsutomu Furuse

Dear Tsutomu,
Thanks your update.
If they need much power reduction then they can consider about the DDR self refresh mode.