Hello Forum Members ,
We are trying to configure to configure Ethernet External switch from 66Ak2h keystone processor.
According to data sheet
3.4.2 MDIO Control Register (MDIO_CONTROL)->
Register 15-0 CLKDIV Clock Divider.
MDCLK frequency = peripheral clock frequency/(CLKDIV+1).
MDCLk required Frequency lies in (1 Mhz -2.5 Mhz).
The doubt is "peripheral clock frequency" mentioned is the System clock supplied from PLL,presently which we are using is 1ghz.
Is my assumption true..?
Thanks in advance.
Regards,
Krishnan
