Other Parts Discussed in Thread: TMS320C6678
Hi Sir
We used TMS320C6678 for development and saw the description in spec as below
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The clock input buffers for CORECLK, DDRCLK, PASSCLK, SRIOSGMIICLK, PCIECLK and MCMCLK
use CVDD as a supply voltage. These clock inputs are not failsafe and must be held in a high-impedance state until
CVDD is at a valid voltage level. Driving these clock inputs high before CVDD is valid could cause damage to the
device. Once CVDD is valid it is acceptable that the P and N legs of these CLKs may be held in a static state (either
high and low or low and high) until a valid clock frequency is needed at that input. To avoid internal oscillation the
clock inputs should be removed from the high impedance state shortly after CVDD is present.
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we would like to use 9DBV0431 as PCIECLK buffer but it does not have high-impedance state for output.
after checking the power management table as below.
Could we set the output pin of 9DBV0431 as LOW for PCIECLK pin before CVDD is valid ?
or other suggestion would be appreciated.
BR
Yimin
