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some problem of C6678 PCIe

user4489731
Intellectual 890 points

Hi,

   I use AMC-PCIe adapter card  to connect DM8168 EVM and C6678 EVM board,DM8168 work as RC and C6678 as EP.I met some problem as following:

  1.After link training success，I have checked some PCIe registers，the value is：

    PL_LINK_CTRL:0x30120（both DM8168 and C6678）

   PL_GEN2:0x20F(both DM8168 and C6678)

   LINK_CAP:0x135422（DM8168），0x35422(C6678)

  LINK_STAT_CTRL:0x30120008(DM8168),0x10120080(C6678)

 According to LINK_STAT_CTRL register，we can see NEGOTIATED_LINK_WD is 0x1,only use x1 lane.both DM8168 and C6678 support x2 lane.what can I do to change x1 mode to x2？

2. To solve problem1, I checked the value of PCIE_SERDES_STS register，the value is 0x00000201，according to document: "Loss of Signal detect of Lane1. Driven high asynchronously when a loss of signal (electrical idle) condition is detected."so I think the problem occured on lane1，why loss of signal detect of lane1？How can I solve it？

3.The problem whether or not related to the boot mode？Do I need to use PCIe boot or others boot mode for C6678？

Regards,

Simon

  • 0
    TI__Guru* 95265 points
    Simon,

    PCIE_SERDES_STS = 0x201 is the real issue that second lane signal is lost. Is this register 0x262015c on C6678 side? What SW is running on 8168 side? Does 8168 has the same register you can check? What SW is running on 6678 side?

    On C6678 PLL side, this is programed to 0x02620358 = 0x1c9, this is nothing you can do for 1 lane or 2 lane. But on the 6678 EVM, you can select where the PCIE reference clock come from:

    wfcache.advantech.com/.../TMDSEVM6678L_Technical_Reference_Manual_2V01_0320.pdf

    See SW5[3] for info. You can try C6678 in PCIE boot mode as well with SW5[3] for on-board or external clock from AMC edge.

    Regards, Eric
  • 0 in reply to lding
    Intellectual 890 points

    Hi,Eric,

    Today，I have read reference document about C6678 PCIe boot in C:\ti\mcsdk_2_01_02_06\tools\boot_loader\examples\pcie\docs，and Import the project from tools\boot_loader\examples\pcie\pcieboot_interrupt\evmc66xxl in CCSv5.I have some questions here;

    1.According to the document，I want to use PCIE Linux Host loader code，and copied pciedemo.c, Makefile,pcieDdrInit_66xx.h, pcieBootCode_66xx.h, pcieInterrupt_66xx.h and post_66xx.h from tools\boot_loader\examples\pcie\linux_host_loader to the linux machine.when I compile pciedemo.c，an error happened：'
    'pcieInterrupt' undeclared (first use in this function)",so I want to know where is “pcieInterrupt” declare？

    2.If question1 be solved，and generate a PCIedemo.ko，should I Edit interrupt_elf2HBin.bat ？if I do this step，shuld I set C6678EVM SW3 as（off，on，on，off）PCIe boot mode and runing the pcieboot_interrupt project on CCS v5？


    3.How about IBL？Is C66xinit.c in C:\ti\mcsdk_2_01_02_06\tools\boot_loader\ibl\src\device\c66x IBL code?how can I use it?

    Best wishes,

    Simon

  • 0 in reply to user4489731
    TI__Guru** 116100 points
    Dear Simon,
    1)
    You have to modify like below in "C:\ti\mcsdk_2_01_02_06\tools\boot_loader\examples\pcie\linux_host_loader\pciedemo.c" and build the *.ko.

    /* Must select which demo to run */
    #define HELLO_WORLD_DEMO 0
    #define POST_DEMO 0
    #define EDMA_INTC_DEMO 1
    #define LOCAL_RESET 0

    /* Must select a platform */
    #define EVMC6678L 1
    #define EVMC6670L 0
    #define EVMC6657L 0

    2)
    Nope.
    You have to modify variables like "C6000_CG_DIR" , location where you have to put *.h, endianness, and TARGET.\
    And then run that windows batch file to generate the *.h in desired location.

    3)
    You have to use IBL code for PCIe boot.

    Please refer to the following TI wiki page.
    processors.wiki.ti.com/.../PCI_Express_(PCIe)_Resource_Wiki_for_Keystone_Devices

    Please let me know if any.
  • 0 in reply to Titusrathinaraj Stalin
    Intellectual 890 points

    Hi，Stalin，

          Thanks for your answer.

           1.I have modified pciedemo.c as you said.and the  error;"pcieInterrupt undeclared"stayed.And then I changed pcieInterrupt to interrupt,I do this change because I found in pcieInterrupt_6678.h,interrupt was declared.and then complied pciedemo.ko successful.

           2.I have found these variables in interrupt_elf2HBin.bat as shown below：

               set C6000_CG_DIR="C:\Program Files\Texas Instruments\C6000 Code Generation Tools 7.4.0"
               set TOOL_DIR="..\..\..\..\..\..\"
               set TARGET=6678
               set ENDIAN=little
               set PATH=%PATH%;%SystemRoot%\system32;%SystemRoot%;

              what does the meaning about C6000_CG_DIR,TOOL_DIR,PATH?How can I change them?

          3.I have read the TI wiki page you suggested，there are some steps to update EEPROM Images.and I have some questions as following：

             1)What is the role of  i2crom_0x51_c667#_le.bin ?

             2)As I have said，I want to use C66xinit.c as IBL code,how can I do it？It is not mentioned in the page.

    Best wishes,

    Simon

  • 0 in reply to user4489731
    TI__Guru** 116100 points

    what does the meaning about C6000_CG_DIR,TOOL_DIR,PATH?How can I change them?


    I have used like below, and I has CGT (code generation tool) in the mentioned ccs path.
    set C6000_CG_DIR="C:\ti\ccsv6\tools\compiler\c6000_7.4.8"


    1)What is the role of i2crom_0x51_c667#_le.bin ?

    Its IBL binary which will forced to boot in I2C and apply the PLL workaround for the DSP and boot as per the boot settings.
  • 0 in reply to Titusrathinaraj Stalin
    Intellectual 890 points

    Hi,Stalin,

          Thank you very much.

           In c66xinit.c,iblPCIeWorkaround(),it is set PL_GEN2 register value is 0x0000000F,and LN_EN field is 0x00,not lane enable x2.Do you think this configuration may result in the problem that I first post？

           Best wishes,

           Simon

  • 0 in reply to user4489731
    TI__Guru* 95265 points

    Simon,

    My understanding is that DM8168 has PCIE x2 lane connector, it connect to AMC-PCIE adaptor card to C6678 EVM with AMC edge.

    For the C6678, we have test with other TI C6678 EVM or TI K2H EVM via breakout card, there is no issue to get x2 lane. For the C6678 EVM with X86 PC, there is also no issue to get x2 lane with IBL code. In the IBL code, we have configuration to pass the PCIE reference clock from PC to EVM.

    For the DM8168 and C6678 pair you are testing, you can just use it is own reference clock as they should be narrow spectrum clock. To narrow down why you have signal loss on lane 1, do you have any setup to verify this is DM8168 side or C6678 side problem? E.g, can DM8168 get x2 with another device? Or the C6678 can get x2 with another device?

    Regards, Eric