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AM57x MMC speed does not go above 45MHz in U-boot

Joshua Vanderpool
Intellectual 550 points

Other Parts Discussed in Thread: TPS659037

I have u-boot 2015.07 and even if the max speed is passed as 96MHz for mmc1 it does not go above 45MHz.

This severely limits the loading of the eMMC on mmc2 which is 8 bits and has a max speed per SR1.1 of 48MHz.

What must be patched to get the speed higher rather than the omap_mmc_init function in board.c?

--- git.orig/board/ti/.../board.c
+++ git/board/ti/.../board.c
@@ -285,8 +285,8 @@ void recalibrate_iodelay(void)
#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_GENERIC_MMC)
int board_mmc_init(bd_t *bis)
{
- omap_mmc_init(0, 0, 0, -1, -1);
- omap_mmc_init(1, 0, 0, -1, -1);
+ omap_mmc_init(0, 0, 96000000, -1, -1);
+ omap_mmc_init(1, 0, 48000000, -1, -1);
return 0;
}

  • 0 in reply to Biser Gatchev-XID
    Intellectual 550 points

    Yes it is built from the processor SDK relased code.

  • 0 in reply to Joshua Vanderpool
    TI__Guru**** 161600 points

    Hi,

    Have a look at drivers/mmc/omap_hsmmc.c, the allowed speed would also depend on the host_caps value:

     cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195;

     cfg->host_caps = host_caps_val & ~host_caps_mask;

     cfg->f_min = 400000;

     if (f_max != 0)

            cfg->f_max = f_max;

     else {

            if (cfg->host_caps & MMC_MODE_HS) {

                  if (cfg->host_caps & MMC_MODE_HS_52MHz)

                            cfg->f_max = 52000000;

                  else

                           cfg->f_max = 26000000;

             } else

                        cfg->f_max = 20000000;

    }

    Therefore when you call the mmc init function you should also change the host_caps_mask & modify the above code fragment as well, if needed.

    Also I see that you want to init mmc0 with 96MHz clock, you should consider the following (described in Section 25.1.1 eMMC/SD/SDIO Features of the device TRM):

      "• Supported data transfer rates:

             – MMCi supports the following SD v3.0 data transfer rates:

                • DS mode (3.3V IOs): up to 12 MBps (24 MHz clock)

                • HS mode (3.3V IOs): up to 24 MBps (48 MHz clock)

                • SDR12 (1.8V IOs): up to 12 MBps (24 MHz clock)

                • SDR25 (1.8V IOs): up to 24 MBps (48 MHz clock)

                • SDR50 (1.8V IOs): up to 48 MBps (96 MHz clock) - MMC1 and MMC3 only

                • DDR50 (1.8V IOs): up to 48 MBps (48 MHz clock) - MMC1 only

                • SDR104 (1.8V IOs) cards can be supported up to 192 MHz clock (96 MBps max) - MMC1 only

            – MMCi supports the Default SD mode 1-bit data transfer up to 24Mbps (3MBps)

            – Only MMC2 supports also the following JC64 v4.5 data transfer rates:

               • Up to 192 MBps in eMMC mode, 8-bit SDR mode (192 MHz clock frequency)

               • Up to 96 MBps in eMMC mode, 8-bit DDR mode (48 MHz clock frequency)"

    Best Regards, 
    Yordan

  • 0 in reply to Yordan Kovachev
    Intellectual 550 points
    I do pass in 96000000 into the init function also the mask is not set as there is no capabilities to mask.
    Does u-boot have the capability with current driver to lower the vdd_sd rail from the TPS659037?

    For the eMMC on mmc2 will it run DDR at 3.3V IO?

    Thanks
  • 0 in reply to Joshua Vanderpool
    TI__Guru**** 161600 points

    Hi,

    Joshua Vanderpool said:
    Does u-boot have the capability with current driver to lower the vdd_sd rail from the TPS659037?

     

    No, I don't see anything indicating this is possible. From the schematic & PMIC datasheet I see that LDO1_OUT (VDD_SD) is configured to output 3.3V. 

    Joshua Vanderpool said:
    For the eMMC on mmc2 will it run DDR at 3.3V IO?

     

    Not sure I understand this. It is recommended to use DDR3L with am572x devices, and this ddr runs at 1.35V, this is how PMIC is set. 

    Best Regards, 
    Yordan

  • 0 in reply to Joshua Vanderpool
    TI__Genius 12850 points
    yes, eMMC on MMC2 can run DDR at 1.8 or 3.3V IO in High-speed JC64 DDR mode. Please refer to chapter 7.32.2 in the datasheet for details

    regards,
    Michael
  • 0 in reply to Yordan Kovachev
    Intellectual 550 points

    The VDD_SD on the Beagle _x15 is on LDO1 and is configurable between .9 and 3.3V.  I think the default is 3.3V, however to reach max speed it must lower the voltage to 1.8V.  Can this be supported in u-boot?  I am currently getting 5MB/s read times from the SD card this makes for a really long loading of the internal eMMC that is on mmc2.

    Thanks

    Josh

  • 0 in reply to Joshua Vanderpool
    TI__Genius 12850 points

    Josh,

    If I understand you correctly you are trying to improve boot time?  What is the SYSBOOT configuration you are using? The MMC interface configuration is done by RBL (when booting from user area: clock=400Khz in identification mode, 10Mhz in Data transfer mode: chapter 33.3.7.6.1 in TRM).  If you need to change it to improve boot time it can only be done through Configuration Header. I have browsed uboot code for CHMMCSD item (refer to TRM chapter 33.3.8.2 Configuration Header) and did not find support for changing eMMC configuration parameters.

    Regards,

    Michael

  • 0 in reply to Michael Shklyarman
    Intellectual 550 points

    Boot time is not the issue it is the loading of a image to the eMMC from the SD card.  When a SD card is present it will boot from this SD card and u-boot will ask if the eMMC should be updated this is where I get a 5MB/s read from the SD to the eMMC.  The process take about 15 minutes.

    So the issue does not lie within the RBL rather support in the u-boot to be able to lower the voltage of the SD interface to 1.8V so either SDR104 mode can be supported or DDR50.

    Josh

  • 0 in reply to Joshua Vanderpool
    TI__Genius 12850 points

    Josh,

    Sorry I misunderstood you objective.

    From browsing uboot sources it looks like it is not possible to change the voltage using configuration setting or command. TO my understanding the PMIC configuration is implemented in drivers/power/palmas.c and is currently hard-coded (line 36). You can try to change it and rebuild the uboot.

    Regards,

    Michael