Hello
I'm using am572x custom board for PCIe endpoint device.
Before merging u-boot, I'm testing in ccsv6.
I configured PRCM, DPLL, APLL, PHY already.
But it access PCIe sub system, below error occurred in ccs console.
I'll attach my source code.
Please let me know what's wrong with my source.
Best regrad,
Jo
//#include <common.h>
//#include <asm/omap_common.h>
#include "ti-am57xx-pci-ep.h"
volatile u32 *PM_L3INIT_PWRSTCTRL = ((volatile u32*)0x4ae07300);
volatile u32 *CM_L3INIT_CLKSTCTRL = ((volatile u32*)0x4a009300);
volatile u32 *CM_L3INIT_OCP2SCP1_CLKCTRL = ((volatile u32*)0x4a0093e0);
volatile u32 *CM_L3INIT_OCP2SCP3_CLKCTRL = ((volatile u32*)0x4a0093e8);
volatile u32 *CM_PCIE_CLKSTCTRL = ((volatile u32*)0x4a0093a0);
static void am57xx_OCP2SCP_ClkEnable(void)
{
//*PM_L3INIT_PWRSTCTRL |= 3;
*PM_L3INIT_PWRSTCTRL = (1<<4) | 3;
*CM_L3INIT_CLKSTCTRL |= 2;
//PCIeSS CLKSTCTRL SW WakeUp
*CM_PCIE_CLKSTCTRL = 0x02 | (*CM_PCIE_CLKSTCTRL & ~0x03);
//OCP2SCP1 enables accessing the PCIe PHY serial configuration
*CM_L3INIT_OCP2SCP1_CLKCTRL = 0x01 | (*CM_L3INIT_OCP2SCP1_CLKCTRL & ~0x3);
//OCP2SCP3 enables accessing the PCIe PHY serial configuration
*CM_L3INIT_OCP2SCP3_CLKCTRL = 0x01 | (*CM_L3INIT_OCP2SCP3_CLKCTRL & ~0x3);
}
volatile u32 *OCP2SCP3_SYSCONFIG = ((volatile u32*)0x4a090010);
volatile u32 *OCP2SCP3_SYSSTATUS = ((volatile u32*)0x4a090014);
volatile u32 *OCP2SCP3_TIMING = ((volatile u32*)0x4a090018);
volatile u32 *CM_CLKMODE_DPLL_PCIE_REF = ((volatile u32*)0x4a008200);
volatile u32 *CM_IDLEST_DPLL_PCIE_REF = ((volatile u32*)0x4a008204);
volatile u32 *CM_AUTOIDLE_DPLL_PCIE_REF = ((volatile u32*)0x4a008208);
volatile u32 *CM_CLKSEL_DPLL_PCIE_REF = ((volatile u32*)0x4a00820C);
volatile u32 *CM_DIV_M2_DPLL_PCIE = ((volatile u32*)0x4a008210);
volatile u32 *CTRL_CORE_SMA_SW_6 = ((volatile u32*)0x4a003C14);
volatile u32 *CM_CLKMODE_APLL_PCIE = ((volatile u32*)0x4a00821c);
volatile u32 *CM_IDLEST_APLL_PCIE = ((volatile u32*)0x4a008220);
volatile u32 *CM_DIV_M2_APLL_PCIE = ((volatile u32*)0x4a008224);
volatile u32 *CM_CLKVCOLDO_APLL_PCIE = ((volatile u32*)0x4a008228);
static void am57xx_PCIeSS1PllConfig(void)
{
//see the PHY pll controller
// module reset
*OCP2SCP3_SYSCONFIG |= 0x02;
//wait for reset done
while(0x01 != (*OCP2SCP3_SYSSTATUS & 0x01));
//division ratio 1, sync2 : 0xf
*OCP2SCP3_TIMING |= (1<<7) | (0xf<<0);
//PCIe DPLL - M&N programming; CLKSEL
*CM_AUTOIDLE_DPLL_PCIE_REF = 0;
//DPLL DIV : 0x09
*CM_CLKSEL_DPLL_PCIE_REF = 0x9 | (*CM_CLKSEL_DPLL_PCIE_REF & ~0xff);
//DPLL Mul
*CM_CLKSEL_DPLL_PCIE_REF = (0x2ee<<8) | (*CM_CLKSEL_DPLL_PCIE_REF & ~(0xfff<<8));
//PCIe DPLL - M2 programming
*CM_DIV_M2_DPLL_PCIE |= 0xf;
//SigmaDelta SD DIV programming
*CM_CLKSEL_DPLL_PCIE_REF = (0x6<<24) | (*CM_CLKSEL_DPLL_PCIE_REF & ~(0xff<<24));
//DPLL Enable
*CM_CLKMODE_DPLL_PCIE_REF |= 0x7; //Lock mode
// Check for DPLL lock status
while(0x01 != (*CM_IDLEST_DPLL_PCIE_REF & 0x01));
//PCIe Tx and Rx Control of ACSPCIe
*CTRL_CORE_SMA_SW_6 = (2<<16) | (*CTRL_CORE_SMA_SW_6 & ~(0X03<<16) );
//Locking APLL to 2.5GHz with 100MHz input
*CM_CLKMODE_APLL_PCIE = (1<<8) | (*CM_CLKMODE_APLL_PCIE & ~(1<<8)); //CLKDIV_BYBASS : 1
*CM_CLKMODE_APLL_PCIE = (0<<7) | (*CM_CLKMODE_APLL_PCIE & ~(1<<7)); //REFSEL : ADPLL 0
*CM_CLKMODE_APLL_PCIE = 1 | (*CM_CLKMODE_APLL_PCIE & ~(0x03)); //apll in ofrce lock mode
//Wait for APLL lock
while(1 != ( *CM_IDLEST_APLL_PCIE &0x01));
}
volatile u32 *PM_PCIE_PCIESS1_WKDEP = ((volatile u32*)0x4ae073b0);
volatile u32 *RM_PCIE_PCIESS1_CONTEXT = ((volatile u32*)0x4ae073b4);
volatile u32 *CM_PCIE_STATICDEP = ((volatile u32*)0x4a0093a4);
volatile u32 *CM_PCIE_PCIESS1_CLKCTRL = ((volatile u32*)0x4a0093b0);
volatile u32 *CM_PCIE_PCIESS2_CLKCTRL = ((volatile u32*)0x4a0093b8);
static void am57xx_PCIeSS1ClkCtrl(void)
{
*CM_PCIE_STATICDEP |= (1<<27) | (1<<26) | (1<<17) | (1<<16) | (1<<14) | (1<<13) | (1<<12) | (1<<7);
*PM_PCIE_PCIESS1_WKDEP |= 1;
//optclk enable
*CM_PCIE_PCIESS1_CLKCTRL = 0x07<<8 | (*CM_PCIE_PCIESS1_CLKCTRL & ~(0x07<<8));
//L3 Init PCIeSS1 CLKCTRL SW Enable
*CM_PCIE_PCIESS1_CLKCTRL = 0x02 | (*CM_PCIE_PCIESS1_CLKCTRL & ~0x03);
while( 0 != (*CM_PCIE_PCIESS1_CLKCTRL&(3<<16)) );
}
static int am57xx_pcie_PRCM_init(void)
{
am57xx_OCP2SCP_ClkEnable();
am57xx_PCIeSS1PllConfig();
am57xx_PCIeSS1ClkCtrl();
return 0;
}
static int am57xx_pcie_ctrl_init(void)
{
volatile u32 *CTRL_CORE_PCIE_CONTROL =((volatile u32*)0x4a003C3C);
*CTRL_CORE_PCIE_CONTROL = 0; //x1 mode
//CONTROL MODULE PWR CTL REG status of PCIeSS1
volatile u32 *CTRL_CORE_PHY_POWER_PCIESS1 =((volatile u32*)0x4a003C40);
*CTRL_CORE_PHY_POWER_PCIESS1 = (0x14<<22) | (*CTRL_CORE_PHY_POWER_PCIESS1 & ~(0x3ff<<22)); // Freq of SYSCLK1 in MHz
*CTRL_CORE_PHY_POWER_PCIESS1 = (0x03<<14) | (*CTRL_CORE_PHY_POWER_PCIESS1 & ~(0xff<<14)); // Powers up phy_TX & RX
//Set PCIeSS1/2 delay count
volatile u32 *CTRL_CORE_PCIE_PCS =((volatile u32*)0x4a003C34);
*CTRL_CORE_PCIE_PCS = (0x96<<16) | (*CTRL_CORE_PCIE_PCS & ~(0xff<<16));
return 0;
}
int am57xx_pcie_L3_Interconnect_init(void)
{
#define FW_ERROR_LOG(base,k) (*(volatile u32*)(base + 0x10*k))
#define FW_LOGICAL_ADDR_ERRLOG(base,k) (*(volatile u32*)(base + 0X04 + 0x10*k))
#define FW_REGUPDATE_CONTROL(base) (*(volatile u32*)(base + 0x40))
#define FW_START_REGION(base,i) (*(volatile u32*)(base + 0x80 + 0x10*i))
#define FW_END_REGION(base,i) (*(volatile u32*)(base + 0x84 + 0x10*i))
#define FW_MRM_PERMISSION_REGION_HIGH(base,j) (*(volatile u32*)(base + 0x8c + 0x10*j))
#define FW_MRM_PERMISSION_REGION_LOW(base,j) (*(volatile u32*)(base + 0x88 + 0x10*j))
//Firewall registers
volatile u32 *DEBUGSS_CT_TBR_FW =((volatile u32*)0x4a224000);
volatile u32 *PCIE1_FW =((volatile u32*)0x4a165000);
volatile u32 *PCIESS2_FW =((volatile u32*)0x4a159000);
typedef struct {
volatile u32 STDHOSTHDR_COREREG;
volatile u32 STDHOSTHDR_VERSIONREG;
volatile u32 STDHOSTHDR_MAINCTLREG;
volatile u32 res[13];
volatile u32 STDERRLOG_SVRTSTDLVL;
volatile u32 STDERRLOG_SVRTCUSTOMLV;
volatile u32 STDERRLOG_MAIN;
volatile u32 STDERRLOG_HDR;
volatile u32 STDERRLOG_MSTADDR;
volatile u32 STDERRLOG_SLVADDR;
volatile u32 STDERRLOG_INFO;
volatile u32 STDERRLOG_SLVOFSLSB;
volatile u32 STDERRLOG_SLVOFSMSB;
volatile u32 STDERRLOG_CUSTOMINFO_MSTADDR;
volatile u32 STDERRLOG_CUSTOMINFO_INFO;
volatile u32 STDERRLOG_CUSTOMINFO_WR;
volatile u32 STDERRLOG_CUSTOMINFO_ADDR;
volatile u32 STDERRLOG_CUSTOMINFO_DECERR;
}*L3MAIN_HOST;
L3MAIN_HOST CLK1_HOST_CLK1_1 = (L3MAIN_HOST)0x44000000;
L3MAIN_HOST CLK1_HOST_CLK1_2 = (L3MAIN_HOST)0x44800000;
L3MAIN_HOST CLK1_HOST_CLK2_1 = (L3MAIN_HOST)0x45000000;
volatile u32 *L3_FLAGMUX_TIMEOUT1_MASK0 = (volatile u32*)0X44805708;
volatile u32 *L3_FLAGMUX_TIMEOUT2_MASK0 = (volatile u32*)0X4480570C;
*L3_FLAGMUX_TIMEOUT1_MASK0 = 0X3FFFFFFF;
*L3_FLAGMUX_TIMEOUT2_MASK0 = 0X001FFFFF;
volatile u32 *PCIE1_TARG = (volatile u32*)0x44003700;
volatile u32 *PCIE2_TARG = (volatile u32*)0x44003800;
volatile u32 *L4_AP_PROT_GROUP_MEMBERS_k = (volatile u32*)0x4a000200;
volatile u32 *L4_AP_PROT_GROUP_ROLES_k = (volatile u32*)0x4a000280;
volatile u32 *L4_AP_REGION_I_L = (volatile u32*)0x4a000300;
return 0;
}
volatile u32 *CTRL_CORE_CONTROL_IO =((volatile u32*)0x4a002554);
volatile u32 *CTRL_CORE_SMA_SW_7 =((volatile u32*)0x4a003c18);
void am57xx_pcie_DeviceMMU2(void)
{
*CTRL_CORE_CONTROL_IO &= ~(1<<20);
*CTRL_CORE_SMA_SW_7 |= (1<<13) | (1<<12) | 3;
volatile u32 *SYSTEM_MMU2_SYSCONFIG =((volatile u32*)0x4881e010);
volatile u32 *SYSTEM_MMU2_SYSSTATUS =((volatile u32*)0x4881e014);
volatile u32 *SYSTEM_MMU2_IRQENABLE =((volatile u32*)0x4881e01c);
volatile u32 *SYSTEM_MMU2_CNTL =((volatile u32*)0x4881e044);
volatile u32 *SYSTEM_MMU2_LOCK =((volatile u32*)0x4881e050);
volatile u32 *SYSTEM_MMU2_LD_LTB =((volatile u32*)0x4881e054);
volatile u32 *SYSTEM_MMU2_CAM =((volatile u32*)0x4881e058);
volatile u32 *SYSTEM_MMU2_RAM =((volatile u32*)0x4881e05c);
volatile u32 *SYSTEM_MMU2_READ_CAM =((volatile u32*)0x4881e068);
volatile u32 *SYSTEM_MMU2_READ_RAM =((volatile u32*)0x4881e06c);
*SYSTEM_MMU2_SYSCONFIG |= (1<<1); //soft reset
while(1 != (*SYSTEM_MMU2_SYSSTATUS&1)); //reset done
*SYSTEM_MMU2_SYSCONFIG |= 1; //auto idle
//configure TLB entries
*SYSTEM_MMU2_CAM = 0x51000000 | (1<<3) | (1<<2) | 0;
//load the physical address of the page
*SYSTEM_MMU2_RAM = 0x51000000;
//specify the TLB entry you wnat to write
*SYSTEM_MMU2_LOCK |= (0 << 4);
//load the specified entry in the TLB
*SYSTEM_MMU2_LD_LTB |= 1;
//enable multihit fault and TLB miss
*SYSTEM_MMU2_IRQENABLE |= (1<<4) | (1);
//enable memory translations
*SYSTEM_MMU2_CNTL |= (1<<1);
}
int am57xx_pcie_ep_init(void)
{
///////////////////////
//Main sequence of PCIe Controllers Initialization
//1. Initialize the DPLL_PCIe_REF ( clock source, dividers, power dependencies) in PRCM
// processed in parent function
//2. Assert a local SW main reset to the PCIe__SS1,2 Controllers
volatile u32 *RM_PCIESS_RSTCTRL =((volatile u32*)0x4ae07310);
volatile u32 *RM_PCIESS_RSTST =((volatile u32*)0x4ae07314);
*RM_PCIESS_RSTCTRL &= ~1;
*RM_PCIESS_RSTCTRL |= 1;
//3. Poll man reset completion status for the PCIe_SS1,2 Controllers
while( 1 != (*RM_PCIESS_RSTST&1) );
//4. Perform tuning of the PCIe phy
//5. Select "PCIe EP" type
volatile u32 *PCIESS1_PCIECTRL_TI_CONF_DEVICE_TYPE = ((volatile u32*)0x51002100);
// volatile u32 *PCIESS2_PCIECTRL_TI_CONF_DEVICE_TYPE = ((volatile u32*)0x51802100);
*PCIESS1_PCIECTRL_TI_CONF_DEVICE_TYPE = 0; //0: EP, 1: Legacy EP, 4: RC
//6. poll to insure fundamental reset has completed
while( 0 !=(*PCIESS1_PCIECTRL_TI_CONF_DEVICE_TYPE & 0x0f) );
//7. Make sure LTSSM_EN is kept by EP's SW at value 0
volatile u32 *PCIESS1_PCIECTRL_TI_CONF_DEVICE_CMD = ((volatile u32*)0x51002104);
//volatile u32 *PCIESS2_PCIECTRL_TI_CONF_DEVICE_CMD = ((volatile u32*)0x51802104);
*PCIESS1_PCIECTRL_TI_CONF_DEVICE_CMD &= ~1;
//8. Initialize EP PCIe controller's core register
//9. clear the IRQ main status register in case raw status is NOT clear
// (to avoid spurious interrupts)
//10. First time enable - PCIe main interrupts.
// Depends on which PCIe protocol events and error events will be handled by application.
//11. Clear the IRQ msi status register in case raw status is NOT clear
// (to avoid spurious interrupts)
//12. Disable both INTx (x=A,B,C,D) and MSI interrupts reception
//13. PCIe controller enables the link. It is supposed that all active EPs attached
// on the PCIe fabric synchronously enable their LTSSM engine with RC.
//14. Local CPU polls until the PCIe Controller link is up
// (i.e. brought into L0- power state)
//15. If PCIECTRL_TI_CONF_IRQ_STATUS_MAIN[3] LINK_UP_EVT has been enabled in step (10),
// this means it should be cleared.
//16. RC host starts link training sequence, negotiation with EPs, enumeration of the EPs,
// and initializes the descriptors per each of the discovered EP functions.
// no need to program this step.
//17. RC only
//18. RC only
//19. EP only. Before EP's application generates a request, the EP application must insure
// that its local BME_EVT status has already been asserted to 1 by the RC host controller.
// The EP must locally clear the BME interrupt, writing BME_EVT_MSG flag to 1(Wr1toClr)
//20. RC only
// EP only. The EP's CPU is notified about remote MEM_SPACE_EN flag assertion
// in a dedicated bit that can be enabled to generate an interrupt.
// The interrupt flag is cleared via writing to 1(Wr1ToClr)
return 0;
}
int am57xx_pcie_global_init(void)
{
//////////////////////////////////////////////////////
//Global initializaion of the PCIe surrounding modules
//////////////////////////////////////////////////////
//1. PRCM//
am57xx_pcie_PRCM_init();
//2. Control modules
am57xx_pcie_ctrl_init();
//3. (Optional) IRQ_CROSSBAR
//4. (Optional) A local INTC
//5. L4 and L3_MAIN interconnects
am57xx_pcie_L3_Interconnect_init();
//6. (Optional) Device MMU2
am57xx_pcie_DeviceMMU2();
am57xx_pcie_ep_init();
return 0;
}
