Omap Setup questions

For OMAPL138 and C6748, PINMUX and PSC settings were same (almost everything).
You can setup using either ARM or DSP core and use it by both.

Yes, I think, either ARM or DSP can setup the EMIFA and able to access by both (need to have some locking mechanism to make sure read/write is not happening simultaneously)

If you are running Linux on ARM core then I think it may not me possible to access the EMIFA location as Linux has virtual memory concept.

Hi Dieter,

Dieter said:

I am moving from a C6748 to an omap L-138 so I can leverage the ARM for extra processing power. I read the documentation on booting up both processors. That is rather straightforward. After they both boot up, do both processors setup:
pin mux settings?
PLL 0 and 1?
power and sleep controller?

Actually, there is an initialization sequence code called gel file which does the memory map of the C6748/OMAPL138 device, initialises PLL0/1, the core frequency, set the DDR frequency, initializes the PSC0/1 ( Power sleep controller) , PINMUX for NAND PIN MUX etc.

The OMAPL138 gel file for OMAPL138 LCDK does all the intialization sequence the same and in addtion to that , it does the wake of the DSP processor.

Dieter said:

If both processors will read from the same EMIF location (an FPGA), will they both setup the chip enables for EMIFA (CE4CFG)? Or does only one processor setup these and they both use them?

For example, in the gel file, it initialises something like below:

hotmenu EMIFA_NAND_PINMUX() {
PSC0_LPSC_enable(0, LPSC_EMIFA);
PINMUX7 = (PINMUX7 & ~0x00FF0FF0) | 0x00110110;
PINMUX8 = 0x11111111;
PINMUX9 = 0x11111111;
PINMUX12 = (PINMUX12 & ~0x0FF00000) | 0x01100000;
EMIFA_ACFG3 |= 0x1;
EMIFA_NANDFCR = (EMIFA_NANDFCR & ~0x30) | 0x12;

GEL_TextOut("\tEMIFA Pins Configured for NAND.\n","Output",1,1,1);
GEL_TextOut("\t---------------------------------------------\n","Output",1,1,1);
}


Once this gel file gets run on the target, ARM will get wake up and the DSP core will get wake up next and it completes all the initialisation. Here the NAND chip will be ready to be accessed by both the ARM and the DSP processor.
If you want to access the NAND chip simultaneously by ARM and DSP, you may have to choose some semaphore mechanisms. That's it.