AM3352: GPIO banks mapped incorrectly

Thomas Snyman

Part Number: AM3352

Hi,

I have a custom board that uses the AM3352 processor. Everything is working except the GPIO pin mapping. The only GPIO bank that works correctly is GPIO 96-127. This is mapped with a modified am335x-evmsk.dts file that I'm using to test my board functionality. If I load the beaglebone black am335x-boneblack.dtb file on the same os and board the GPIO address is correct. Below is a bit of detail of my system.

Linux: Custom built with yocto

dts: Modified am335x-evmsk.dts (attached below)

Have tried with ti-linux-processor-sdk as well with same results. Thus concluding that it must be my dts file.

Output from board with BBB dtb:

root@beaglebone:~# cat /sys/kernel/debug/gpio
GPIOs 0-31, platform/44e07000.gpio, gpio:
 gpio-6   (                    |cd                  ) in  lo IRQ

GPIOs 32-63, platform/4804c000.gpio, gpio:
 gpio-53  (                    |?                   ) out lo
 gpio-54  (                    |?                   ) out lo
 gpio-55  (                    |?                   ) out hi
 gpio-56  (                    |?                   ) out lo

GPIOs 64-95, platform/481ac000.gpio, gpio:

GPIOs 96-127, platform/481ae000.gpio, gpio:

As you can see the address is correct. Output with custom dtb file:

GPIOs 0-31, platform/481ac000.gpio, gpio:

GPIOs 32-63, platform/44e07000.gpio, gpio:
 gpio-38  (                    |cd                  ) in  lo IRQ

GPIOs 64-95, platform/4804c000.gpio, gpio:

GPIOs 96-127, platform/481ae000.gpio, gpio:
 gpio-114 (                    |sysfs               ) out hi    
 gpio-115 (                    |sysfs               ) out hi    
 gpio-116 (                    |sysfs               ) out hi

Here the first three GPIO blocks are incorrect. But I am able to control GPIO's 96-127.

DTS:

/dts-v1/;

#include "am33xx.dtsi"
#include <dt-bindings/pwm/pwm.h>
#include <dt-bindings/interrupt-controller/irq.h>

/ {
	model = "TI AM335x EVM-SK";
	compatible = "ti,am335x-evmsk", "ti,am33xx";
	
	cpus {
		cpu@0 {
			cpu0-supply = <&vdd1_reg>;
		};
	};

	memory {
		device_type = "memory";
		reg = <0x80000000 0x10000000>; /* 256 MB */
	};

	vbat: fixedregulator@0 {
		compatible = "regulator-fixed";
		regulator-name = "vbat";
		regulator-min-microvolt = <5000000>;
		regulator-max-microvolt = <5000000>;
		regulator-boot-on;
	};
	
	panel {
		compatible = "ti,tilcdc,panel";
		pinctrl-names = "default", "sleep";
		pinctrl-0 = <&lcd_pins_default>;
		status = "okay";
		panel-info {
			ac-bias           = <255>;
			ac-bias-intrpt    = <0>;
			dma-burst-sz      = <16>;
			bpp               = <16>;
			fdd               = <0x80>;
			sync-edge         = <0>;
			sync-ctrl         = <1>;
			raster-order      = <0>;
			fifo-th           = <0>;
		};
		display-timings {
			320x240 {
				hactive         = <320>;
				vactive         = <240>;
				hback-porch     = <5>;
				hfront-porch    = <58>;
				hsync-len       = <47>;
				vback-porch     = <11>;
				vfront-porch    = <23>;
				vsync-len       = <2>;
				clock-frequency = <12000000>;
				hsync-active    = <0>;
				vsync-active    = <0>;
			};
		};
	};
};

&am33xx_pinmux {

	lcd_pins_default: pinmux_lcd_pins_default {
		pinctrl-single,pins = <
            0xe0 ( PIN_OUTPUT | MUX_MODE0 ) /* (U5) lcd_vsync.lcd_vsync */
            0xe4 ( PIN_OUTPUT | MUX_MODE0 ) /* (R5) lcd_hsync.lcd_hsync */
            0xe8 ( PIN_OUTPUT | MUX_MODE0 ) /* (V5) lcd_pclk.lcd_pclk */
            0xec ( PIN_OUTPUT | MUX_MODE0 ) /* (R6) lcd_ac_bias_en.lcd_ac_bias_en */
            0xa0 ( PIN_OUTPUT | MUX_MODE0 ) /* (R1) lcd_data0.lcd_data0 */
            0xa4 ( PIN_OUTPUT | MUX_MODE0 ) /* (R2) lcd_data1.lcd_data1 */
            0xa8 ( PIN_OUTPUT | MUX_MODE0 ) /* (R3) lcd_data2.lcd_data2 */
            0xac ( PIN_OUTPUT | MUX_MODE0 ) /* (R4) lcd_data3.lcd_data3 */
            0xb0 ( PIN_OUTPUT | MUX_MODE0 ) /* (T1) lcd_data4.lcd_data4 */
            0xb4 ( PIN_OUTPUT | MUX_MODE0 ) /* (T2) lcd_data5.lcd_data5 */
            0xb8 ( PIN_OUTPUT | MUX_MODE0 ) /* (T3) lcd_data6.lcd_data6 */
            0xbc ( PIN_OUTPUT | MUX_MODE0 ) /* (T4) lcd_data7.lcd_data7 */
            0xc0 ( PIN_OUTPUT | MUX_MODE0 ) /* (U1) lcd_data8.lcd_data8 */
            0xc4 ( PIN_OUTPUT | MUX_MODE0 ) /* (U2) lcd_data9.lcd_data9 */
            0xc8 ( PIN_OUTPUT | MUX_MODE0 ) /* (U3) lcd_data10.lcd_data10 */
            0xcc ( PIN_OUTPUT | MUX_MODE0 ) /* (U4) lcd_data11.lcd_data11 */
            0xd0 ( PIN_OUTPUT | MUX_MODE0 ) /* (V2) lcd_data12.lcd_data12 */
            0xd4 ( PIN_OUTPUT | MUX_MODE0 ) /* (V3) lcd_data13.lcd_data13 */
            0xd8 ( PIN_OUTPUT | MUX_MODE0 ) /* (V4) lcd_data14.lcd_data14 */
            0xdc ( PIN_OUTPUT | MUX_MODE0 ) /* (T5) lcd_data15.lcd_data15 */
		>;
	};
    
    emmc_pins_default: pinmux_emmc_pins_default {
        pinctrl-single,pins = <
			0x80 (PIN_INPUT_PULLUP | MUX_MODE2) /* gpmc_csn1.mmc1_clk */
			0x84 (PIN_INPUT_PULLUP | MUX_MODE2) /* gpmc_csn2.mmc1_cmd */
			0x00 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad0.mmc1_dat0 */
			0x04 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad1.mmc1_dat1 */
			0x08 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad2.mmc1_dat2 */
			0x0c (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad3.mmc1_dat3 */
			0x10 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad4.mmc1_dat4 */
			0x14 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad5.mmc1_dat5 */
			0x18 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad6.mmc1_dat6 */
			0x1c (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad7.mmc1_dat7 */
        >;
            //0x74 (PIN_INPUT_PULLUP | MUX_MODE7) /* gpmc_wpn.gpio0_31 */
			//0x80 (PIN_INPUT_PULLUP | MUX_MODE2) /* gpmc_csn1.mmc1_clk */
			//0x84 (PIN_INPUT_PULLUP | MUX_MODE2) /* gpmc_csn2.mmc1_cmd */
			//0x00 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad0.mmc1_dat0 */
			//0x04 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad1.mmc1_dat1 */
			//0x08 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad2.mmc1_dat2 */
			//0x0c (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad3.mmc1_dat3 */
    };

	cpsw_default: cpsw_default {
		pinctrl-single,pins = <
			/* Slave 1 */
			0x110 (PIN_INPUT_PULLUP | MUX_MODE0)	/* mii1_rxerr.mii1_rxerr */
			0x114 (PIN_OUTPUT_PULLDOWN | MUX_MODE0)	/* mii1_txen.mii1_txen */
			0x118 (PIN_INPUT_PULLUP | MUX_MODE0)	/* mii1_rxdv.mii1_rxdv */
			0x11c (PIN_OUTPUT_PULLDOWN | MUX_MODE0)	/* mii1_txd3.mii1_txd3 */
			0x120 (PIN_OUTPUT_PULLDOWN | MUX_MODE0)	/* mii1_txd2.mii1_txd2 */
			0x124 (PIN_OUTPUT_PULLDOWN | MUX_MODE0)	/* mii1_txd1.mii1_txd1 */
			0x128 (PIN_OUTPUT_PULLDOWN | MUX_MODE0)	/* mii1_txd0.mii1_txd0 */
			0x12c (PIN_INPUT_PULLUP | MUX_MODE0)	/* mii1_txclk.mii1_txclk */
			0x130 (PIN_INPUT_PULLUP | MUX_MODE0)	/* mii1_rxclk.mii1_rxclk */
			0x134 (PIN_INPUT_PULLUP | MUX_MODE0)	/* mii1_rxd3.mii1_rxd3 */
			0x138 (PIN_INPUT_PULLUP | MUX_MODE0)	/* mii1_rxd2.mii1_rxd2 */
			0x13c (PIN_INPUT_PULLUP | MUX_MODE0)	/* mii1_rxd1.mii1_rxd1 */
			0x140 (PIN_INPUT_PULLUP | MUX_MODE0)	/* mii1_rxd0.mii1_rxd0 */
		>;
	};

	davinci_mdio_default: davinci_mdio_default {
		pinctrl-single,pins = <
			/* MDIO */
			0x148 (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0)	/* mdio_data.mdio_data */
			0x14c (PIN_OUTPUT_PULLUP | MUX_MODE0)			/* mdio_clk.mdio_clk */
		>;
	};
    
    mmc1_pins: pinmux_mmc1_pins {
		pinctrl-single,pins = <
			0x160 (PIN_INPUT | MUX_MODE7) /* GPIO0_6 */
		>;
	};

    
    microsd_pins_default: pinmux_microsd_pins_default {
        pinctrl-single,pins = <
            0x100 ( PIN_INPUT | MUX_MODE0 ) /* (G17) mmc0_clk.mmc0_clk */
            0x104 ( PIN_OUTPUT | MUX_MODE0 ) /* (G18) mmc0_cmd.mmc0_cmd */
            0xfc ( PIN_INPUT | MUX_MODE0 ) /* (G16) mmc0_dat0.mmc0_dat0 */
            0xf8 ( PIN_INPUT | MUX_MODE0 ) /* (G15) mmc0_dat1.mmc0_dat1 */
            0xf4 ( PIN_INPUT | MUX_MODE0 ) /* (F18) mmc0_dat2.mmc0_dat2 */
            0xf0 ( PIN_INPUT | MUX_MODE0 ) /* (F17) mmc0_dat3.mmc0_dat3 */
            0x160 ( PIN_INPUT | MUX_MODE5 ) /* (C15) spi0_cs1.mmc0_sdcd */
        >;
    };
    

    i2c0_pins_default: pinmux_i2c0_pins_default {
        pinctrl-single,pins = <
            0x18c ( PIN_INPUT | MUX_MODE0 ) /* (C16) I2C0_SCL.I2C0_SCL */
            0x188 ( PIN_INPUT | MUX_MODE0 ) /* (C17) I2C0_SDA.I2C0_SDA */
        >;
    };

    uart0_pins_default: pinmux_uart0_pins_default {
        pinctrl-single,pins = <
            0x170 ( PIN_INPUT | MUX_MODE0 ) /* (E15) uart0_rxd.uart0_rxd */
            0x174 ( PIN_OUTPUT | MUX_MODE0 ) /* (E16) uart0_txd.uart0_txd */
        >;
    };


    uart1_pins_default: pinmux_uart1_pins_default {
        pinctrl-single,pins = <
            0x180 ( PIN_INPUT | MUX_MODE0 ) /* (D16) uart1_rxd.uart1_rxd */
            0x184 ( PIN_OUTPUT | MUX_MODE0 ) /* (D15) uart1_txd.uart1_txd */
        >;
    };


    uart2_pins_default: pinmux_uart2_pins_default {
        pinctrl-single,pins = <
            0x150 ( PIN_INPUT | MUX_MODE1 ) /* (A17) spi0_sclk.uart2_rxd */
            0x154 ( PIN_OUTPUT | MUX_MODE1 ) /* (B17) spi0_d0.uart2_txd */
        >;
    };


    uart4_pins_default: pinmux_uart4_pins_default {
        pinctrl-single,pins = <
            0x70 ( PIN_INPUT | MUX_MODE6 ) /* (T17) gpmc_wait0.uart4_rxd */
            0x74 ( PIN_OUTPUT | MUX_MODE6 ) /* (U17) gpmc_wpn.uart4_txd */
        >;
    };
    
    gpio0_pins_default: pinmux_gpio0_pins_default {
        pinctrl-single,pins = <
            0x20 ( PIN_INPUT | MUX_MODE7 ) /* (U10) gpmc_ad8.gpio0[22] */
            0x24 ( PIN_INPUT | MUX_MODE7 ) /* (T10) gpmc_ad9.gpio0[23] */
            0x28 ( PIN_INPUT | MUX_MODE7 ) /* (T11) gpmc_ad10.gpio0[26] */
            0x2c ( PIN_INPUT | MUX_MODE7 ) /* (U12) gpmc_ad11.gpio0[27] */
        >;
    };
    
    gpio1_pins_default: pinmux_gpio1_pins_default {
        pinctrl-single,pins = <
            0x30 ( PIN_INPUT | MUX_MODE7 ) /* (T12) gpmc_ad12.gpio1[12] */
            0x34 ( PIN_INPUT | MUX_MODE7 ) /* (R12) gpmc_ad13.gpio1[13] */
            0x38 ( PIN_INPUT | MUX_MODE7 ) /* (V13) gpmc_ad14.gpio1[14] */
            0x3c ( PIN_INPUT | MUX_MODE7 ) /* (U13) gpmc_ad15.gpio1[15] */
            0x40 ( PIN_INPUT | MUX_MODE7 ) /* (R13) gpmc_a0.gpio1[16] */
            0x48 ( PIN_INPUT | MUX_MODE7 ) /* (U14) gpmc_a2.gpio1[18] */
            0x78 ( PIN_INPUT | MUX_MODE7 ) /* (U18) gpmc_be1n.gpio1[28] */
        >;
    };

    gpio3_pins_default: pinmux_gpio3_pins_default {
        pinctrl-single,pins = <
            0x1a0 ( PIN_INPUT | MUX_MODE7 ) /* (B12) mcasp0_aclkr.gpio3[18] */
            0x1a4 ( PIN_INPUT | MUX_MODE7 ) /* (C13) mcasp0_fsr.gpio3[19] */
            0x1a8 ( PIN_INPUT | MUX_MODE7 ) /* (D13) mcasp0_axr1.gpio3[20] */
        >;
    };

    spi1_pins_default: pinmux_spi1_pins_default {
        pinctrl-single,pins = <
            0x190 ( PIN_OUTPUT | MUX_MODE3 ) /* (A13) mcasp0_aclkx.spi1_sclk */
            0x194 ( PIN_OUTPUT | MUX_MODE3 ) /* (B13) mcasp0_fsx.spi1_d0 */
            0x198 ( PIN_OUTPUT | MUX_MODE3 ) /* (D12) mcasp0_axr0.spi1_d1 */
            0x19c ( PIN_OUTPUT | MUX_MODE3 ) /* (C12) mcasp0_ahclkr.spi1_cs0 */
        >;
    };
};

&spi1 {
    pinctrl-names = "default";
    pinctrl-0 = <&spi1_pins_default>;

    status = "okay";
	
	lcd-control@0 {
        compatible = "linux,spidev";
        spi-max-frequency = <1000000>;
        reg = <0>;
	};
};

&gpio0 {
    pinctrl-names = "default";
    pinctrl-0 = <&gpio0_pins_default>;
    
    status = "okay";
};

&gpio1 {
    pinctrl-names = "default";
    pinctrl-0 = <&gpio1_pins_default>;
    
    status = "okay";
};

&gpio3 {
    pinctrl-names = "default";
    pinctrl-0 = <&gpio3_pins_default>;
    
    status = "okay";
};

&uart0 {
	pinctrl-names = "default";
	pinctrl-0 = <&uart0_pins_default>;

	status = "okay";
};

&uart1 {
	pinctrl-names = "default";
	pinctrl-0 = <&uart1_pins_default>;

	status = "okay";
};

&uart2 {
	pinctrl-names = "default";
	pinctrl-0 = <&uart2_pins_default>;

	status = "okay";
};

&uart4 {
	pinctrl-names = "default";
	pinctrl-0 = <&uart4_pins_default>;

	status = "okay";
};

&i2c0 {
	pinctrl-names = "default";
	pinctrl-0 = <&i2c0_pins_default>;

	status = "okay";
	clock-frequency = <400000>;

	tps: tps@2d {
		reg = <0x2d>;
	};
};

&wkup_m3_ipc {
	ti,needs-vtt-toggle;
	ti,vtt-gpio-pin = <7>;
	ti,scale-data-fw = "am335x-evm-scale-data.bin";
};

#include "tps65910.dtsi"

&tps {
	vcc1-supply = <&vbat>;
	vcc2-supply = <&vbat>;
	vcc3-supply = <&vbat>;
	vcc4-supply = <&vbat>;
	vcc5-supply = <&vbat>;
	vcc6-supply = <&vbat>;
	vcc7-supply = <&vbat>;
	vccio-supply = <&vbat>;

	regulators {
		vrtc_reg: regulator@0 {
			regulator-always-on;
		};

		vio_reg: regulator@1 {
			regulator-always-on;
		};

		vdd1_reg: regulator@2 {
			/* VDD_MPU voltage limits 0.95V - 1.26V with +/-4% tolerance */
			regulator-name = "vdd_mpu";
			regulator-min-microvolt = <912500>;
			regulator-max-microvolt = <1351500>;
			regulator-boot-on;
			regulator-always-on;
		};

		vdd2_reg: regulator@3 {
			/* VDD_CORE voltage limits 0.95V - 1.1V with +/-4% tolerance */
			regulator-name = "vdd_core";
			regulator-min-microvolt = <912500>;
			regulator-max-microvolt = <1150000>;
			regulator-boot-on;
			regulator-always-on;
		};

		vdd3_reg: regulator@4 {
			regulator-always-on;
		};

		vdig1_reg: regulator@5 {
			regulator-always-on;
		};

		vdig2_reg: regulator@6 {
			regulator-always-on;
		};

		vpll_reg: regulator@7 {
			regulator-always-on;
		};

		vdac_reg: regulator@8 {
			regulator-always-on;
		};

		vaux1_reg: regulator@9 {
			regulator-always-on;
		};

		vaux2_reg: regulator@10 {
			regulator-always-on;
		};

		vaux33_reg: regulator@11 {
			regulator-always-on;
		};

		vmmc_reg: regulator@12 {
			regulator-min-microvolt = <3300000>;
			regulator-max-microvolt = <3300000>;
			regulator-always-on;
		};
	};
};

&cpsw_emac0 {
	phy_id = <&davinci_mdio>, <0>;
	phy-mode = "mii";
};

&mac {
	pinctrl-names = "default";
	pinctrl-0 = <&cpsw_default>;
	status = "okay";
};

&davinci_mdio {
	pinctrl-names = "default";
	pinctrl-0 = <&davinci_mdio_default>;
	status = "okay";
};

&mmc1 {
    vmmc-supply = <&vmmc_reg>;
	bus-width = <0x4>;
	pinctrl-names = "default";
	pinctrl-0 = <&mmc1_pins>;
	cd-gpios = <&gpio0 6 GPIO_ACTIVE_LOW>;
	status = "okay";
};

&mmc2 {
	vmmc-supply = <&vmmc_reg>;
	bus-width = <8>;
	pinctrl-names = "default";
	pinctrl-0 = <&emmc_pins_default>;
	status = "okay";
};

&sham {
	status = "okay";
};

&aes {
	status = "okay";
};

&lcdc {
      status = "okay";
};

&rtc {
	system-power-controller;
};

The other pins that I have muxed also work, The LCD, SPI, I2C0, and uarts have no problem. I it must be something with my dts and the GPIO's.

Any help or advice is greatly appreciated, and thank in advance.

over 8 years ago

0 Biser Gatchev-XID over 8 years ago

TI__Guru**** 393215 points

The software team have been notified. They will respond here.

0 Thomas Snyman over 8 years ago

Prodigy 110 points

Here is some more information that might help. I have de-compiled both the beaglebone black and my custom DTB files to see if there is a difference and what it might be. Searching for the GPIO block the first change that I see is below:

BBB DTB:

pinmux_gpio0_pins_default {
	pinctrl-single,pins = <0x20 0x2f 0x24 0x2f 0x28 0x2f 0x2c 0x2f>;
	linux,phandle = <0x31>;
	phandle = <0x31>;
};

Custom DTB:

pinmux_gpio0_pins_default {
	pinctrl-single,pins = <0x20 0x2f 0x24 0x2f 0x28 0x2f 0x2c 0x2f>;
	linux,phandle = <0x30>;
	phandle = <0x30>;
};

It seems that the phandle between the two compiled versions is different. I don't know if this is how it is suppose to be. I have gone through my files and the am33xx.dtsi file to see what might set the phandle. But no luck thus far. This is the only change that I can see when you search both files for GPIO0. I have attached the two decompiled DTS files in case this helps. I will see what happens if I modify the phandle in the decompiled dtb and compile it again. Any help on why this happened would be great.

dtbs.zip

0 Thomas Snyman over 8 years ago in reply to Thomas Snyman

Prodigy 110 points

Updated Post. Accidentally posted the same snippet twice. Actually second phandle for my custom dtb file is 0x30

0 Thomas Snyman over 8 years ago in reply to Thomas Snyman

Prodigy 110 points

Hi, Another update.

I have manged to trigger and read the GPIO's with a bit of a workaround. This is not ideal as its a bit limited, but at least got the hardware tested.

I removed all the GPIO pin muxing from the dtb, except for GPIO's 96 - 127 as they where correct. This then basically leaves the GPIO's unclaimed once Linux has booted. I then use sysfs to export and set up my GPIO's and read or trigger them. If I don't map GPIO blocks 0 and 0. The mapping seems to be correct:

GPIOs 0-31, platform/44e07000.gpio, gpio:
 gpio-6   (                    |cd                  ) in  lo IRQ
 gpio-22  (                    |sysfs               ) out hi    
 gpio-26  (                    |sysfs               ) out hi    
 gpio-27  (                    |sysfs               ) out hi    

GPIOs 32-63, platform/4804c000.gpio, gpio:
 gpio-44  (                    |sysfs               ) out lo    
 gpio-45  (                    |sysfs               ) out hi    
 gpio-46  (                    |sysfs               ) in  lo    
 gpio-47  (                    |sysfs               ) in  lo    
 gpio-48  (                    |sysfs               ) in  lo    
 gpio-50  (                    |sysfs               ) out lo    
 gpio-60  (                    |sysfs               ) in  hi    

GPIOs 64-95, platform/481ac000.gpio, gpio:

GPIOs 96-127, platform/481ae000.gpio, gpio:
 gpio-114 (                    |sysfs               ) out hi    
 gpio-115 (                    |sysfs               ) out hi    
 gpio-116 (                    |sysfs               ) out hi    

GPIOs 506-511, platform/tps65910-gpio, tps65910, can sleep:

As you can see I managed to export a bunch of GPIO's and have been testing.

I still need to do it properly in the dtb file as I need to register them as certain devices and triggers and all that. I will also need to mux PWM1 and PWM2, that I have not yet found a way to do with sysfs, and it might cause the same problems if I try from the dtb.

I will keep this updated as I find something new. But again. any help or direction would be great.

PS: changing the phandle was a dumb call on my part. That is to uniquely identify a device node. Should have googled before posting.

Best regards,

Thomas

0 Thomas Snyman over 8 years ago in reply to Thomas Snyman

Prodigy 110 points

Hi,

Have anyone from TI managed to take a look at this? Is there any more details that I can send in?

Regards,
Thomas

0 Thomas Snyman over 8 years ago in reply to Thomas Snyman

Prodigy 110 points

Hi, Is there anyone that is able to help me with this?

0 Kemal R. Shakir over 8 years ago in reply to Thomas Snyman

TI__Guru 55345 points

Hello Thomas,

I suspect the phandle property that is manipulating the gpio mapping, what is your final conclusion on this? Also, which Processor SDK version you use? I will check this on my end?

Best regards,
Kemal

0 Thomas Snyman over 8 years ago in reply to Kemal R. Shakir

Prodigy 110 points

Hi Kemal,

I'm using "ti-processor-sdk-linux-am335x-evm-03.02.00.05-Linux-x86-Install" for my testing. I did not change the phandle as from what I could see it was something that gets assigned and not something the dts assigns.

The best I have so far is that when I add GPIO maps for certain pins it causes the mapping to be incorrect. I generated the maps from the TI could muxing tool.

0 Yordan Kovachev over 8 years ago in reply to Thomas Snyman

TI__Guru**** 161600 points

Hi,

I tested this on my BBB, running TI SDK 03.01.00.06 (kernel 4.4.19), which should be quite similar to sdk-linux-am335x-evm-03.02.00.05. I use the prebuilt dtb file, without any additions to the dtb, and I succeeded to get output from gpio0_26 & gpio1_14 P8_16 & P8_14 on the P8 expansion header:

root@am335x-evm:/sys/class/gpio# cd gpio46

root@am335x-evm:/sys/class/gpio/gpio46# ls

active_low device direction edge power subsystem uevent value

root@am335x-evm:/sys/class/gpio/gpio46# cat direction

root@am335x-evm:/sys/class/gpio/gpio46# echo out > direction

root@am335x-evm:/sys/class/gpio/gpio46# cat value

root@am335x-evm:/sys/class/gpio/gpio46# echo 1 > value

Steps for gpio26 are the same:

root@am335x-evm:/sys/class/gpio# echo 26 > export
root@am335x-evm:/sys/class/gpio# ls
export gpio26 gpiochip0 gpiochip32 gpiochip64 gpiochip96 unexport
root@am335x-evm:/sys/class/gpio# cd gpio26/
root@am335x-evm:/sys/class/gpio/gpio26# ls
active_low device direction edge power subsystem uevent value
root@am335x-evm:/sys/class/gpio/gpio26# echo out > direction

root@am335x-evm:/sys/class/gpio/gpio26# echo 1 > value
root@am335x-evm:/sys/class/gpio/gpio26# echo 0 > value

And I saw the gpio pins toggle. You're modifying the kernel dtb right?

So my suggestion is to check your u-boot dts for duplication of the gpio pins you use.. Latest ti kernels have dts in the u-boot as well (arch/arm/dts/where most of the pinmuxing happens), so make sure it does not mess with the gpios you use.

Best Regards,
Yordan

0 Thomas Snyman over 8 years ago in reply to Yordan Kovachev

Prodigy 110 points

Hi Yordan,

Thank you for the reply. Yes, I have a custom dtb file that is a modified am335x-evmsk.dtb file. I will take a look at the u-boot dtb files and modify those as well to and get both the same. Is the u-boot dtb file appended to the u-boot image when I compile u-boot? I will need to do some more reading on this.

If I use the pre-built dtb files I also get it to work correctly, or if I don't add my GPIO definitions.

I will update as soon as I have a look into the u-boot dtb. Hopefully that will solve the problem.

Best regards,
Thomas

0 Yordan Kovachev over 8 years ago in reply to Thomas Snyman

TI__Guru**** 161600 points

Hi Thomas,

Is the u-boot dtb file appended to the u-boot image when I compile u-boot?

Yes, it is appended in the u-boot image.
Just for my info, can you share the steps you use to build your kernel & dtb? You can use the top level makefile:
cd ~/ti-processor-sdk-linux-am335x-evm-03.02.00.05
make linux /* to compile the linux kernel & dtb */
make u-boot /* for u-boot */
Or at least inspect the Makefile & Rules.make to see what you need to set up your environment correctly.

Best Regards,
Yordan

0 Thomas Snyman over 8 years ago in reply to Yordan Kovachev

Prodigy 110 points

Hi,

Thanks for the answer. I use basically the process you showed I go to the sdk root directory and run 'make linux' after I have changed the dts file in the board suppor/linux directory. I do not rebuild u-boot every time I modify the dts file and build a new dtb. Might this cause a problem?

This is the first time I have ever worked with device trees so I am stumbling a bit through it.

0 Bart Bogaerts over 8 years ago in reply to Thomas Snyman

Prodigy 30 points

Hello,

Currently it seems that we have the same problem ;-(
We hope that this is not a problem that we use this discussion.

We also created custom dts file based on the am335x-boneblack.dts file and added the GPIO settings as defined in the documentation.

extract out of the dts file

        gpio1_pins: pinmux_gpio1_pins {
	        pinctrl-single,pins = <
        	        0x34 ( PIN_OUTPUT_PULLUP | MUX_MODE7 ) /* (R12) gpmc_ad13.gpio1[13] */
                        0x38 ( PIN_OUTPUT_PULLUP | MUX_MODE7 ) /* (V13) gpmc_ad14.gpio1[14] */
                        0x3c ( PIN_OUTPUT_PULLUP | MUX_MODE7 ) /* (U13) gpmc_ad15.gpio1[15] */
	        >;
        };
        gpio2_pins: pinmux_gpio2_pins {
	        pinctrl-single,pins = <
                        0x8c ( PIN_OUTPUT_PULLUP | MUX_MODE7 ) /* (V12) gpmc_clk.gpio2[1] */
	        >;
&gpio0 {
    status = "okay";
};

&gpio1 {
    pinctrl-names = "default";
    pinctrl-0 = <&gpio1_pins>;
    status = "okay";

    p13 {
        gpio-hog;
        gpios = <13 GPIO_ACTIVE_HIGH>;
        output-high;
        line-name = "SoftwareReset";
    };
    p14 {
        gpio-hog;
        gpios = <14 GPIO_ACTIVE_HIGH>;
        output-high;
                line-name = "ResetNTR";
    };  
    /*p15 {
        gpio-hog;
        gpios = <15 GPIO_ACTIVE_HIGH>;
        output-high;
                line-name = "Reset emmc";
    };*/  
};

&gpio2 {
    pinctrl-names = "default";
    pinctrl-0 = <&gpio2_pins>;
    status = "okay";

    p1 {
        gpio-hog;
        gpios = <1 GPIO_ACTIVE_HIGH>;
        output-high;
        line-name = "Reset SLICS";
    };
};

&gpio3 {
    status = "okay";
};

After compiling dts into dtb and loading on the custom board we noticed that the GPIO offsets are remapped ?

unknown:~# cat /sys/kernel/debug/gpio
GPIOs 0-31, platform/44e07000.gpio, gpio:
 gpio-6   (                    |cd                  ) in  lo IRQ

GPIOs 32-63, platform/481ae000.gpio, gpio:

GPIOs 64-95, platform/4804c000.gpio, gpio:
 gpio-77  (                    |SoftwareReset       ) out hi
 gpio-78  (                    |ResetNTR            ) out hi

GPIOs 96-127, platform/481ac000.gpio, gpio:
 gpio-97  (                    |Reset SLICS         ) out hi

We expect that we have :

unknown:~# cat /sys/kernel/debug/gpio
GPIOs 0-31, platform/44e07000.gpio, gpio:
 gpio-6   (                    |cd                  ) in  lo IRQ

GPIOs 32-63, platform/4804c000.gpio, gpio:

GPIOs 64-95, platform/481ac000.gpio, gpio:

GPIOs 96-127, platform/481ae000.gpio, gpio:

We use a yocto environment to build a image for our custom board.

unknown:~# uname -a
Linux 8fxs 4.4.11-yocto-standard #10 PREEMPT Thu Jan 26 15:06:40 CET 2017 armv7l armv7l armv7l GNU/Linux

For us it is not clear what is going wrong ?

Thanks in advance.

Regards,
Bart Bogaerts

0 Thomas Snyman over 8 years ago in reply to Bart Bogaerts

Prodigy 110 points

Hi Bart,

Once you remove the pin mapping for your GPIO's I guess you get the same result as me. Where you can at least trigger them from sysfs (/sys/class/gpio/export).

I'm busy testing the rest of my hardware and getting a demo going for radio emissions testing. But once I'm done with that I will look into u-boot and see if the dtb file in that might be causing a problem when handing over to the kernel. Unfortunately I will only be getting to that next week. But If you want to try it would be greatly appreciated. Else next week I will start working on that.

I'll keep posting my findings here.

Good luck,
Thomas

0 Bart Bogaerts over 8 years ago in reply to Thomas Snyman

Prodigy 30 points

Hello Thomas,

Indeed if no GPIO pin mappings results in correct working via the sysfs.

But we want to use setting the defaults via the dts file mechanism. We are looking forward to the solution ;-)

Regards,
Bart

0 AnBer over 8 years ago in reply to Bart Bogaerts

TI__Mastermind 30110 points

Bart,

Yordan asked for some info above:
https://e2e.ti.com/support/arm/sitara_arm/f/791/p/568315/2086881#2086881

It does not seem that you use the TI processor SDK Linux.
Could you try with the TI processor SDK setup?
It will install the kernel and GCC tool chain. This way you could compare with what you get.
The SDK 3.02 based on kernel 4.4.32 is located at:
http://www.ti.com/tool/PROCESSOR-SDK-AM335X

Anthony

0 Bart Bogaerts over 8 years ago in reply to AnBer

Prodigy 30 points

Hello Anthony,

Indeed we are not using the TI processor SDK linux. We are using the Yocto linux distribution. Version = YP Core - Krogoth 2.1.2

We were wondering which SDK is present into this yocto linux distribution any idea how we can figure out which TI processor SDK version is present into this yocto distribution? Or is there no relationship ?

We can give it a try using the TI processor SDK linux. Is there something changed about the GPIO pin mappipngs treatment into the new SDK?

Regards,
Bart Bogaerts

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