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what is the peripheral_base_addr for serdes PCIE?

user3460508
Prodigy 110 points
Other Parts Discussed in Thread: TCI6638K2K

Hi, i'm working on serdes_sb code. In struct CSL_SERDES_LANE_ENABLE_PARAMS, there is uint32_t peripheral_base_addr. I can find the peripheral_base_addr for 10GE is 0x02F00000 +0x600 in the source code,but can't find the peripheral_base_addr for PCIE,COULD YOU TELL ME what is the peripheral_base_addr for PCIE? I find 0x02F00000 is XGE Config,mentioned in TCI6638K2K Data Manual. but don't understand the meaning of offset 0x600. what does this offset mean? Thanks a lot in advance

  • 0
    TI__Guru**** 161600 points
    Hi,

    You can check the base address from the Data Manual, Table 8-1. Device Memory Map Summary for TCI6638K2K, and then the specific register offset from the 10 Gigabit Ethernet Switch Subsystem User Guide for KeyStone II Devices.

    In you case from data sheet, 10 GE base address is 0x02F00000 and the offset 00600h corresponds to Port 1 PCS-R module, according to Table 3-1 10 Gigabit Ethernet Subsystem Modules from the user guide (www.ti.com/.../spruhj5.pdf).

    Best Regards,
    Yordan
  • 0 in reply to Yordan Kovachev
    Prodigy 110 points
    Hi

    Thank you for your reply.
    How about the peripheral_base_addr for PCIE?
    I find there is PCIE config (0x21800000) in TCI6638K2K , but there is nothing like Port 1 PCS-R module in XGE.
    I already tried 0x21800000 as Serdes_lane_enable_params.peripheral_base_addr. but The code is doing the infinite loop in serdes_diag_test_init-> CSL_SerdesLaneEnable-> CSL_SerdesPCIe_Lane_Enable-> CSL_SerdesGetStatus to Check the status, but never get the right the status
    So i wonder if there is a offset like XGE'S Port 1 PCS-R module