66AK2H14: Input frequency for system PLL Clock inputs

Madhu Sharma

Part Number: 66AK2H14

HI,

For the System clock inputs of 66AK2H14 ( ALTCORECLK, ARMCLK, DDR3ACLK, etc) , the hardware design guide ( in table 4, SPRABV0) suggests to use inputs within range 40 to 312.5 Mhz.

Can I use Clock of any frequency within this ?

Actually I'm planning to use 156.25Mhz each. Is there any specific preferred clock inputs for which processor performance is better?

Thanks & Regards,

Madhu.

over 8 years ago

0 Senthilkumar Srinivasan over 8 years ago

TI__Mastermind 43660 points

Madhu,

Please refer table 8-27 & 8-28 in the data manual for recommended system PLL and ARM PLL input clocks.

Regards,
Senthil

0 Rahul Prabhu over 8 years ago

TI__Guru** 116170 points

Madhu,

I recommend that you look at the device datasheet (Table 8-27 )for supported values table. Only 8 values in that range are supported so make sure that you pick accordingly. All the 8 values have been tested in design and 156.25 is an supported value in that table.

To minimize the software changes and validation effort on your side, we recommend usually recommend that you follow the clocking used on EVM spec unless there is a strong reason to make a different design choice. This will allow you to bring up TI provided software fairly easily while bringing up your custom hardware.

For EVM spec, you can look at schematics on page 5 here:
wfcache.advantech.com/.../K2H_K2EVM-HK_SCH_A104_Rev4_0.pdf

Hope this helps.

Regards,
Rahul

0 Madhu Sharma over 8 years ago in reply to Rahul Prabhu

Expert 2915 points

Hi,

Thanks for the reply.

The table 8.27 is for System PLL and 8.28 is for ARM PLL.

Whether System PLL and Main PLL are same?

Regards,
Madhu.

0 Rahul Prabhu over 8 years ago in reply to Madhu Sharma

TI__Guru** 116170 points

Yes, System PLL is same as Main PLL. It looks like it needs to be corrected in the literature for consistency.

Regards,
Rahul

0 Madhu Sharma over 8 years ago in reply to Rahul Prabhu

Expert 2915 points

Hi,

Thanks for the reply.

Table 8-27 & 8-28 in the data manual give recommended system PLL and ARM PLL input clocks. Similarly, Is there any recommended clock inputs for DDR3PLLs & PASS PLL??

Regards,

Madhu.

0 Rahul Prabhu over 8 years ago in reply to Madhu Sharma

TI__Guru** 116170 points

Madhu,

Please refer to section 3 in the Hardware design guide for Keystone II device. this has the details for all valid clock values for the PLL:
www.ti.com/.../sprabv0.pdf

Regards,
Rahul

0 Madhu Sharma over 8 years ago in reply to Rahul Prabhu

Expert 2915 points

Hi,

The hardware user guide gives only the clock input range, between 40Mhz and 312.5Mhz. Can I give clock input of any frequency which is within this range?

Regards,

Madhu.

0 Madhu Sharma over 8 years ago in reply to Madhu Sharma

Expert 2915 points

Hi,

Can anyone please answer the above question??

Thanks in advance.

Regards,
Madhu.

0 Senthilkumar Srinivasan over 8 years ago in reply to Madhu Sharma

TI__Mastermind 43660 points

Madhu,

As mentioned in the earlier post, the clock values given in the hardware design guide are only validated on TI design. Going with other clock values would lead to software change and additional validation at your end.

Regards,
Senthil

0 Madhu Sharma over 8 years ago in reply to Senthilkumar Srinivasan

Expert 2915 points

Hi Senthil,

Thanks for the reply.

It looks like hardware design guide doesn't specify any clock input to DDR3A_CLK and DDR3B_CLK. Only supported input clock range is provided.

The EVM uses 100MHz for these inputs. I would like to know is there any other tested/ validated clock inputs for these pins.

Regards,

Madhu.

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66AK2H14: Input frequency for system PLL Clock inputs