hi,
I want to run 3.125Gbps SRIO,I have 250MHz reference clock. lane0 and lane1 is X2 ;lane2 and lane3 is X2.
I use SRIO_LoopbackDioIsrexampleproject in pdk6678.
I modify some code of function int32_t SrioDevice_init (void) in device_srio_loopback.c .
// CSL_SRIO_SetLoopbackMode(hSrio, 0);
// CSL_SRIO_SetLoopbackMode(hSrio, 1);
// CSL_SRIO_SetLoopbackMode(hSrio, 2);
// CSL_SRIO_SetLoopbackMode(hSrio, 3);
CSL_SRIO_SetNormalMode(hSrio, 0);
CSL_SRIO_SetNormalMode(hSrio, 1);
CSL_SRIO_SetNormalMode(hSrio, 2);
CSL_SRIO_SetNormalMode(hSrio, 3);
// /* Assuming the link rate is 2500; program the PLL accordingly. */
// CSL_BootCfgSetSRIOSERDESConfigPLL (0x233);
//
// /* Configure the SRIO SERDES Receive Configuration. */
// CSL_BootCfgSetSRIOSERDESRxConfig (0, 0x004404a5);
// CSL_BootCfgSetSRIOSERDESRxConfig (1, 0x004404a5);
// CSL_BootCfgSetSRIOSERDESRxConfig (2, 0x004404a5);
// CSL_BootCfgSetSRIOSERDESRxConfig (3, 0x004404a5);
//
// /* Configure the SRIO SERDES Transmit Configuration. */
// CSL_BootCfgSetSRIOSERDESTxConfig (0, 0x001807a5);
// CSL_BootCfgSetSRIOSERDESTxConfig (1, 0x001807a5);
// CSL_BootCfgSetSRIOSERDESTxConfig (2, 0x001807a5);
// CSL_BootCfgSetSRIOSERDESTxConfig (3, 0x001807a5);
// Set the link rate is 3.125G; program the PLL accordingly. */
CSL_BootCfgSetSRIOSERDESConfigPLL (0x065);
/* Configure the SRIO SERDES Receive Configuration. */
CSL_BootCfgSetSRIOSERDESRxConfig (0, 0x004404a5);
CSL_BootCfgSetSRIOSERDESRxConfig (1, 0x004404a5);
CSL_BootCfgSetSRIOSERDESRxConfig (2, 0x004404a5);
CSL_BootCfgSetSRIOSERDESRxConfig (3, 0x004404a5);
/* Configure the SRIO SERDES Transmit Configuration. */
CSL_BootCfgSetSRIOSERDESTxConfig (0, 0x001807a5);
CSL_BootCfgSetSRIOSERDESTxConfig (1, 0x001807a5);
CSL_BootCfgSetSRIOSERDESTxConfig (2, 0x001807a5);
CSL_BootCfgSetSRIOSERDESTxConfig (3, 0x001807a5);
/* Configure the path mode for the ports. */
for(i = 0; i < 4; i++)
CSL_SRIO_SetPLMPortPathControlMode (hSrio, i, 3);
#ifndef SIMULATOR_SUPPORT
/* This code checks if the ports are operational or not. The functionality is not supported
* on the simulator. */
//for(i = 0; i < 4; i++)
//Tj : set lane A and B is X2; set lane C and D is X2;
while (CSL_SRIO_IsPortOk (hSrio, 0) != TRUE);
// while (CSL_SRIO_IsPortOk (hSrio, i) != TRUE);
#endif
the function will stuck in
while (CSL_SRIO_IsPortOk (hSrio, 0) != TRUE);
I read
For example, for 3.125Gbps data, a refclk of 312.5Mhz or 156.25Mhz or 125MHz is needed.
in page 36 in KeyStone Architecture Serial Rapid IO （SPRUGW1B）.
Can 6670 run SRIO 3.125Gbps with SRIOSGMIICLK 250MHz?
