Reference
SPRUFM4G – TMS320C674x/OMAP-L1x Processor Serial Peripheral Interface (SPI) User's Guide
· 2.5.1.2 Chip Select Hold Time
· Table 24. SPI Delay Register (SPIDELAY) Field Descriptions
· Figure 30. Example: tT2CDELAY = 4 SPI Module Clock Cycles
I suspect that the Transmit-end-to-chip-select-inactive-delay (T2CDELAY) equation application description and example figure in the User’s Guide may be in error, and I requesting clarification/verification.
The text in section 2.5.1.2 and the text for the T2CDELAY register field description in Table 24 both indicate that if the phase = 0, there will be an additional delay of 0.5 SPIx_CLK period over that specified by the given equation.
Is it possible that the aforementioned text should refer to an additional delay of 0.5 SPI module clock cycle period over that specified by the given equation?
Also the text for the T2CDELAY register field description example in Table 24 refers to a VBUSPCLK entity.
For consistency and clarity, shouldn’t the T2CDELAY register field description example text utilize or reference the SPI module clock period in lieu of VBUSPCLK?
The supporting diagram (Figure 30) for the T2CDELAY register field description example suggests a 4 SPI module clock cycle (160 ns) delay yet there appears to be a 3½ SPI module clock cycle delay.
Is it also possible that the aforementioned supporting diagram should indicate a 4½ SPI module clock cycle (180 ns) delay since it appears to be a phase = 0 and polarity = 0 example if we incur an additional delay of 0.5 SPI module clock cycle period in lieu of the stated additional delay of 0.5 SPIx_CLK period?
