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AM5716: DSP L2 EDC scrubbing

Keith Elliott
Intellectual 890 points
Part Number: AM5716

I am working with the C66x CorePac on two products, one with the AM5716 and one with the C6674. I was hoping to get some clarification regarding the operating procedure of the L2 EDC. Section 11.3.2 of sprugw0c states that the setup procedure for the L2 EDC is as follows.

  1. Disable EDC
  2. Clear EDC Errors
  3. Scrub Memory with IDMA
  4. Enable EDC
  5. Run
  6. Periodically scrub memory with IDMA (optional)

I've read through the Memory Scrubbing Technique section (11-12) but am still unclear on certain aspects. My questions are as follows.

  1. The memory scrubbing procedure appears to provide two options, writing 128 bits that are 128 bit aligned to ensure correct parity and valid bits, and writing to the entire used section of L2. Which one of these is referred to by step 3 of the above procedure?
  2. Is there a specific time when these procedure should be performed? At the beginning of the application or in the bootloader?
  3. The bootloader for the one product (C6674) is running on the first core. Since one core's L2 is accessible by another core can I perform the memory scrubbing from a core to which the L2 being scrubbed doesn't belong? (e.g. can Core 0 scrub Core 1's L2 memory?)
  4. What does "optional" mean in step 6 above? What are the consequences of not performing periodic scrubbing of the memory?
  5. Can you clarify whether or not scrubbing removes the errors reported in the L2 EDC status register?

  • 0
    TI__Guru**** 393215 points
    The DSP experts have been notified. They will respond here.
  • 0 in reply to Biser Gatchev-XID
    Intellectual 890 points
    Thank you, have you heard back from the DSP experts?
  • 0 in reply to Keith Elliott
    TI__Mastermind 26205 points
    I am so sorry.... I have escalated this post...
  • 0 in reply to Rogerio Almeida
    TI__Mastermind 23125 points
    Keith,

    sorry for the delay, I got derailed to other tasks. to your questions:

    1.The memory scrubbing procedure appears to provide two options, writing 128 bits that are 128 bit aligned to ensure correct parity and valid bits, and writing to the entire used section of L2. Which one of these is referred to by step 3 of the above procedure?
    [Jian] Step 3 in the L2 EDC setup sequence refers to all address range of the L2 that is configured as RAM. As parity bits are to be generated for all memory block.

    2.Is there a specific time when these procedure should be performed? At the beginning of the application or in the bootloader?
    [Jian] The procedure shall be performed at bootloader or any time the CorePac is reset. Running at beginning of application is not mandatory, as CorePac does not get reset per application.

    3.The bootloader for the one product (C6674) is running on the first core. Since one core's L2 is accessible by another core can I perform the memory scrubbing from a core to which the L2 being scrubbed doesn't belong? (e.g. can Core 0 scrub Core 1's L2 memory?)
    [Jian] I assume you would use EDMA instead of Core_1's IDMA, via the SDMA port. Yes the SDMA access (must be aligned to 128b) will be able to scrub the Core_1 L2 RAM. There is a caveat to this, that if a single-bit error is corrected the EDMA, the data in the memory will be altered, but Core_1's L1 may not be coherent to L2, though the L1 content is still logically correct. Again, each core's own IDMA is the preferred option.

    4.What does "optional" mean in step 6 above? What are the consequences of not performing periodic scrubbing of the memory?
    [Jian] The net effect of scrubbing is to reduce to probability of double-bit error. For systems that are up for a long time, say, years, there may be a single-bit error happened, all read access will be correct, as the single-bit error is always corrected by the parity bit. But over time by probability, another single-bit error may happen in the same 128b quanta, then a non-correctable double bit error happens.

    5.Can you clarify whether or not scrubbing removes the errors reported in the L2 EDC status register?
    [Jian] Not automatically. Instead, a single-bit correction happens, the event got logged into the EDC event counter registers. It is up to the software to clear them via writing to L2EDCMD register bits, when the EDC errors happens and interrupt the DSP.

    let me if there are further questions.
    Jian