CCS/TDA2EXEVM: Try to Load .elf file on Cortex A15 of TDA2EX

Harshalkumar Shinde

Intellectual 320 points

Part Number: TDA2EXEVM

Tool/software: Code Composer Studio

Hi,

On TDA2EX board First we work on IPU2 processor, For that in Linker file we use the address

MEMORY
{
IPU_RAM: org = 0x00000000 len = 0x3000
DDR3_IPU2: org = 0x83f00000 len = 0x9FD000

}

Its working Fine. .elf get loaded properly and executed properly

For A15 i changed DDR3_IPU2 address to 0x402f0000

Now i want to load same code for A15, Connect the Target A15 then run the script to enable the PRCM module same did for IPU2, but when i try to load same elf i get the following error

CortexA15_0: File Loader: Verification failed: Values at address 0x00000000 do not match Please verify target memory and memory map.
CortexA15_0: GEL: File: D:\TDA2EX_FICOSA_WS\001_Os_UNIPHASE_ARM\04_Testing\01_Em\Test_App_TDA2EX\App_Os_AlarmandCounters\obj\App_Os_AlarmandCounters.elf: a data verification error occurred, file load failed.
CortexA15_0: Unable to terminate memory download: NULL buffer pointer at 0x3aa4

Please suggest If their is any changes in Linker File or Compiler Flag or Linker Flag to load the elf on A15

Following Compiler Flag used

CCFLAGS= --silicon_version=7M4 --abi=eabi

Thanks,

Harshalkumar Shinde

over 7 years ago

0 Alex Bashkov over 7 years ago

TI__Genius 13425 points

Hello,

You can't use the IPU file as is for A15. Can you try modifying your file to initialize the memories for A15? Like so:

MEMORY
{

    OCMC_RAM1 :  o = 0x40300000,  l = 0x00080000  /* 512kB L3 OCMC RAM1 */
    OCMC_RAM2 :  o = 0x40400000,  l = 0x00100000  /* 1MB L3 OCMC RAM2 */
    OCMC_RAM3 :  o = 0x40500000,  l = 0x00100000  /* 1MB L3 OCMC RAM3 */
    DDR0 :       o = 0x80000000,  l = 0x40000000  /* 1GB external DDR Bank 0 */
    DDR1 :       o = 0xC0000000,  l = 0x40000000  /* 1GB external DDR Bank 1 */

}

I am attaching another liner file for reference.https://e2e.ti.com/cfs-file/__key/communityserver-discussions-components-files/791/0842.TDA2x.lds

Thanks,
Alex

0 Rishabh Garg over 7 years ago

TI__Guru 55685 points

Hi Harshal,

In addition to what Alex said DDR is not located at 0x402f0000 .
Also A15 does not see any RAM at 0x0 which can be loaded using CCS unlike M4 which has RAM.
Please refer to chapter 2 section "MPU Memory Map".

Regards,
Rishabh

0 Harshalkumar Shinde over 7 years ago in reply to Rishabh Garg

Intellectual 320 points

Hello Rishabh and Alex,

Thanks For the Reply. When i am using the following address

IPU_RAM: org = 0x40300000 len = 0x3000
DDR3_IPU2: org = 0x80000000 len = 0xA00000

it's work properly. i.e from the Cinit() function main() function get called.

0 Alex Bashkov over 7 years ago in reply to Harshalkumar Shinde

TI__Genius 13425 points

Harshalkumar,

Thanks for confirming those addresses fix your issues. We will close this thread then.

thanks
Alex

0 Rishabh Garg over 7 years ago in reply to Harshalkumar Shinde

TI__Guru 55685 points

Hi Harshal,

One point to note.
OCMC_RAM1 is at address 0x40300000 and not IPU RAM.
IPU RAM is at address 0x0 (IPU's view).

Regards,
Rishabh

0 Harshalkumar Shinde over 7 years ago in reply to Rishabh Garg

Intellectual 320 points

Hello Rishabh,

Ok, It means Reset address and stating of Vector table address for MPU A15 is at 0x40300000. Is it?

Thanks,
Harshalkumar Shinde.

0 Rishabh Garg over 7 years ago in reply to Harshalkumar Shinde

TI__Guru 55685 points

Hi,

No OCMC_RAM is a shared resource. Any CPU can use it.

Regards,
Rishabh

0 Rishabh Garg over 7 years ago in reply to Rishabh Garg

TI__Guru 55685 points

Hi,

Do you have additional questions on this topic? If not, please confirm the previous post answered your question.

Thanks & Regards,
Rishabh Garg

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CCS/TDA2EXEVM: Try to Load .elf file on Cortex A15 of TDA2EX