Compiler/TDA2EXEVM: How to handle the nest interrupt in Cortex-A15?

kiran vidhate

Part Number: TDA2EXEVM

Tool/software: TI C/C++ Compiler

Hi,

In Cortex A15 -MPU : We are starting three timer ,Timer3,Timer9,Timer11 at time with Enable the interrupt for all 3.We have configured the priority Higher for timer11 ,time9 then timer3. When use one timer it work properly.When we start two timer like timer3 and timer9 at time we had got interrupt of timer3 then timer9. Before existing for Timer3 Isr subroutine of timer 9 interrupt came .Timer 9 interrupt was not properly exit from ISR exit routine.

How to Handle the nested ISR in cortex A15?

over 8 years ago

0 Prasad Jondhale over 8 years ago

TI__Mastermind 27743 points

Kiran,

Are you using common ISR for all these timer interrrupts?
Can you please elaborate"Timer 9 interrupt was not properly exit"?

0 kiran vidhate over 8 years ago in reply to Prasad Jondhale

Intellectual 255 points

hi Prasad,
Yes ,I am using all three timer interrupt .I have Started same time with some difference in Load Value and when i was excuting my timer3 interrupt subroutine at time my time 9 interrupt is hitting Timer9 interrupt subroutine.after completion of Timer9 subroutine it wont goes to Timer3 Isr subroutine because LR I am getting LR of IRQ Handler .Because of this my PC goes to abort Handler routine.

0 Prasad Jondhale over 8 years ago in reply to kiran vidhate

TI__Mastermind 27743 points

Hello Kiran,

Please refer to CSL_armGicCallBackFxn in pdk\packages\ti\csl\src\ip\arm_gic\V0\csl_armGicAux.h and pdk\packages\ti\csl\src\ip\arm_gic\V0\csl_a15_intr.asm files.
Here interrupts are handled in system mode to handle interrupt nesting. User mode LR is stored by callback function and restored after ISR call.

0 Prasad Jondhale over 8 years ago in reply to Prasad Jondhale

TI__Mastermind 27743 points

Also same is summarized in below ARM post
infocenter.arm.com/.../index.jsp

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Compiler/TDA2EXEVM: How to handle the nest interrupt in Cortex-A15?