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RTOS/AM4378: Cache and EDMA performance

Marko Kastelic
Expert 1770 points

Part Number: AM4378

Tool/software: TI-RTOS

Hi,

I am quite new in the big "machines", so I need some suggestions regarding to understanding cache and EDMA performance.

EDMA:

What are benefits of big or smal intermediate transfer block size?

What is "recommended"/usual choice of block size?

Any documentation which mention this characteristic?

How activity of EDMA on DDR bus affect cache?

Cache:
In case of using EDMA, Edma3_CacheInvalidate() function is needed. It this function just "discard" region of memory from cache or it also disable cache?
Is possible to "force" cache to start collecting/load data from DDR before program actually need this data?
For example:
In interrupt EDMA(transfer complete) I wish signal to cache -> start caching data which EDMA was just copy.
When task for processing data will start, data will be already in cache and CPU don't need wait for data.
Am I too optimistic? :)

Regards, Mare


 
 

  • 0
    TI__Guru**** 393215 points
    The RTOS team have been notified. They will respond here.
  • 0 in reply to Biser Gatchev-XID
    TI__Guru* 95265 points
    Hi,

    Please check the AM437x technical Reference Manual Chapter 10 for details. The purpose of using EDMA is to transfer big block of data without occupy CPU. The transfer size is controlled by DBS (data burst size) configurable by CTRL_TPTC_CFG register. It can be 16, 32, 64 to 128 bytes. Then when configure the transfer, in the OPT and Param set, you have A-sync, A-B sync and A count size and B count size. If you have a big block of data to transfer, then DBS = 128 and A count at least of 128 are suggested to better use of the EDMA. The transfer controller breaks big data chunk into DBS for each transfer. If you data comes from some peripheral with limited bus width or the data block is small, you can still set DBS = 128 but A count would be same as the number of bytes you want to transmit a time. This mainly helps offload CPU.

    Edma3_CacheInvalidate() function just "discard" region of memory from cache and it doesn't disable cache. You need to do cache invalidate AFTER the EDMA transfer completion for CPU to get the right data.

    Regards, Eric