This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

AM4376: LPDDR2 compliance test fails

Part Number: AM4376


Hi,

It seems that our customer has failed in the compliance test of LPDDR2.
The item of tDH: Input Hold Time (Differential - Vref based) of DM0 signal is Fail.

The DM signal rises almost simultaneously with the rise of the DQS signal.
It seems that it does not satisfy the DM signal hold time only at the first rise of the DQS signal.

In the case of such a symptom, can it be solved by changing EMIF register setting value?
If that is possible, please tell me that register.

Best Regards,
Shigehiro Tsuda