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TMS320C6678: Question about address translation by SES MPAX with PCIe interface

Snaku Lee26
Intellectual 310 points
Part Number: TMS320C6678

Hi experts,

I have a question about address translation by SES MPAX with PCIe interface.

I want to translate logical address from PCIe to DDR3 by SES MPAX on C6678 EVM (the DDR3 size is 1GB), C6678 PCIe is endpoint, and PC is host. I setup the mapping in SES MPAX 2nd segmeng for PCIe (i.e. SES_MPAXH_B_1 and SES_MPAXL_B_1) which tranlates 0x5000_0000 to 0x8_0000_0000, then I tried to access C6678's DDR3 from PC host via PCIe BAR 1 (BAR 1 inbound offset is 0x5000_0000), but the translation is not work.

I change the mapping in SES MPAX which tranlates 0xE000_0000 to 0x8_0000_0000, and BAR 1 inbound offset change to 0xE000_0000, the translation is works.

Does the SES MPAX only translate the logical region 0x8000_0000-0xFFFF_FFFF ?  Because the wiki say "Any accesses through the SES port that does not address either the external memory logical space or the EMIF memory mapped registers result in an addressing error returned to the requesting master."

Regards,

Snaku

  • 0
    TI__Guru**** 161600 points
    Hi Snaku,

    I've consulted the design team.

    Best Regards,
    Yordan
  • 0 in reply to Yordan Kovachev
    TI__Guru* 95265 points
    Hi,

    Does the SES MPAX only translate the logical region 0x8000_0000-0xFFFF_FFFF ? This is not true. We have use case to translation a portion of MSMC (0x0cxx_xxxx) into DDR region to make it un-cached.

    Can you try translate 0x0c00_0000 (or similar) into DDR 0x8_0000_0000 and configure BAR1 to 0x0c00_0000, before translation, you should see the data written into MSMC from PC. Will you see data in DDR after translation?

    Regards, Eric
  • 0 in reply to lding
    Intellectual 310 points

    Hi Eric,

    No, I can't access the DDR after I setup the translation with 0x0C00_0000, below picture is my configuration, I use PCIE BAR1 to access 0x0C00_0000, and SES_MPAX_B_3 to translate 0x0C00_0000 into 0x8_3C00_0000.

    When I read 0x0C00_0000 via PCIE BAR1, I still get the data in 0x0C00_0000. And I can access 0xE000_0000 and 0xF000_0000 via BAR3 and BAR4 correctly with this configuration, could you help me to check them. Thanks for your support.

    Regards,

    Snaku

  • 0 in reply to Snaku Lee26
    TI__Guru* 95265 points

    Hi,

    The PCIE inbound translation looks right. In the MPAX setting, PCIE master privilege ID is 11, can you double check if the offset to 0x0bc0_0000 is correct? Also, E000_0000 is mapped to 8:2000:0000 and F000_0000 mapped to 8:3000:0000. How do you know they are correctly mapped? By default, there is also 2GB mapping of 8000:0000 to 0x8:0000:0000. So, it is possible that E000:0000 is mapped to 8:6000:0000, and given this is 1GB DDR, the address is 8:2000:0000?

    Regards, Eric

  • 0 in reply to lding
    Intellectual 310 points

    Hi Eric,

    I check the SES_MPAX register address, it is correct, because the SES_MPAX register offset at the MSMC is 0x600, and one PrivID has eight pair MPAX segment, so the 11th PrivID MPAX segment address is 0x0BC0_0000 + 0x600 + (64*11) = 0x0BC0_08C0. If the address of SES_MPAX_B_1 is correct, then it has higher priority than SES_MPAX_B_0 (the default one), so your assumption should not be happen, right?

    And I do another test, I use SES_MPAX_B_0 to translate 0xE000_0000 to 0x8_0000_0000, and I write data to 0xE000_0000 via PCIE BAR3, the data appear at 0x8000_0000 in memory browser, so I think the translation is works on 0xE000_0000.

    Regards,

    Snaku

  • 0 in reply to Snaku Lee26
    TI__Guru* 95265 points
    Hi,

    We recently has a similar issue with another customer who wanted to translate DDR3A 0x8:0000:0000 to logical address lower than 0x8000:0000 with MPAX with EDMA master. It didn't worked, but it worked with logical address above 0x8000:0000. From the discussion with design team, the DDR3A can only be translated to address above 0x8000:0000 for master like EDMA, or PCIE (your case).

    I knew the answer is very late, I want to put the info here for customer may meet the same issue again. Sorry for this!

    Regards, Eric