TMS320C6657: C6657 SRIO: maximum packet size for NWRITE

Hi,

What is the maximum packet size for NWRITE?

See Section 2.3.2.2.1 WRITE Transactions of the Serial RapidIO (SRIO) for Keystone Devices User's Guide (www.ti.com/.../sprugw1b.pdf). It says:
"There can be 16 payload packets with payload size up to 256B and 16 header packets without payload. "

Does it require byte alignment like multiple 8 bytes?

Again see the user guide, section 2.3.2.2.3 Packet Segmentation:
"The LSU handles two types of segmentation of outbound requests. First, when the Byte_Count of Read/Write requests exceeds 256 Bytes. Second, when Read/Write request RapidIO address is non-64b aligned. In both cases, the outgoing request must be broken up into multiple RapidIO request packets. For example, the CPU wants to perform a 1KB store operation to an external RapidIO device. After setting up the LSU registers, the CPU simply performs one write to the LSU_Reg5 command register. The peripheral hardware then segments the store operation into four RapidIO write packets of 256B each, and calculates the 64b-aligned RapidIO address, WRSIZE, and WDPTR as required for each packet. The LSU registers can not be released until all posted request packets are passed to the TX FIFOs. Alternatively, for non-posted operations, such as CPU loads, all packet responses must be received before the LSU registers are released"

Also have a look at Section 2.3.3 Message Passing.

Best Regards,
Yordan