Part Number: PROCESSOR-SDK-AM437X
Tool/software: TI-RTOS
I find that the interrupt lines of the PHY chip are changed by checking my hardware, the interrupt line of port 1 is connected to F24(GPIO5_9), the interrupt line of port 2 is connected to D25(GPIO5_8). Compared to to the original design of AM437x Starter Kit Evaluation Module, the interrupt line of port 1 is connected to B7, the interrupt line of port 2 is connected to A7.
My question is, if I want to implement the TCP/UDP communication by the two ethernet port in the NDK/TIRTOS, What changes do software need to do about the interrupt line changed?
