Part Number: DRA71
Tool/software: Linux
Team
In the following kernel commit the mmc driver was replaced
We are using kernel 4.4.91 provided by Android O SDK. It is using the following driver
dra7.dtsi
mmc2: mmc@480b4000 {
compatible = "ti,dra7-hsmmc", "ti,omap4-hsmmc";
reg = <0x480b4000 0x400>;
interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
ti,hwmods = "mmc2";
ti,needs-special-reset;
dmas = <&sdma_xbar 47>, <&sdma_xbar 48>;
dma-names = "tx", "rx";
status = "disabled";
sd-uhs-sdr25;
sd-uhs-sdr12;
mmc-hs200-1_8v;
mmc-ddr-1_8v;
};
Our overlay custom.dtsi
#include "dra72x.dtsi"
...
&mmc2 {
status = "okay";
pinctrl-names = "default", "hs", "ddr_1_8v", "hs200_1_8v";
pinctrl-0 = <&mmc2_pins_default>;
pinctrl-1 = <&mmc2_pins_hs>;
pinctrl-2 = <&mmc2_pins_ddr &mmc2_iodelay_ddr_conf>;
pinctrl-3 = <&mmc2_pins_hs200 &mmc2_iodelay_hs200_conf>;
bus-width = <8>;
max-frequency = <200000000>;
ti,non-removable;
vmmc-supply = <&mmc_reg>;
/delete-property/ sd-uhs-sdr12;
/delete-property/ sd-uhs-sdr25;
};
Our MMC2 (phy port) detects
255|famp:/ # cat /sys/kernel/debug/mmc1/ios
clock: 200000000 Hz
vdd: 7 (1.65 - 1.95 V)
bus mode: 2 (push-pull)
chip select: 0 (don't care)
power mode: 2 (on)
bus width: 3 (8 bits)
timing spec: 9 (mmc HS200)
signal voltage: 0 (1.80 V)
driver type: 0 (driver type B)
famp:/ # cat /sys/kernel/debug/mmc1/
clock ios mmc1:0001/ regs
famp:/ # cat /sys/kernel/debug/mmc1/regs
mmc1:
sdio irq mode polling
ctx_loss: 1
regs:
CON: 0x00108620
PSTATE: 0x01f00000
HCTL: 0x00000b10
SYSCTL: 0x000e0047
IE: 0x00000000
ISE: 0x00000000
CAPA: 0x24e90080
Our eMMC card is eMMC5.1 backward compatible to eMMC4.5&5.0.
We are having any issue with read speed, we get (sequential read) 100MB/s aprox only, vs 200MB/s from datasheet.
Write speed is ok 23MB/s aprox (25MB/s is the datasheet speed)
Is there any constraint in the currently used MMC driver version?
We have to update to newer one?
Regards
