66AK2G12: Hardware design differences between K2G Speed grades

Hi Jeff,

Besides the CVDD voltage there shouldn't be any differences between these two parts.
So if you plan to run 66AK2G12ABY100 at 600MHz you should be fine.

Consider sections 2.2.1 PMIC & 2.2.2 Discrete Power Supplies from the Schematic Checklist: www.ti.com/.../sprac54a.pdf
and section 7.3 Power Distribution Network (PDN) Implementation Guidance from the device Datasheet.

Best Regards,
Yordan

Hi Jeff,
Besides the change to 1V you will need need to re-run the power consumption model to determine if your power supply solution will provided enough current. Also review your PDN design to see if the number, value and position of your bypass capacitors is sufficient. You need to review your thermal analysis to determine if additional airflow or a heat sink is necessary. You also need to consider whether you are going to keep your DDR3L solution at 800MT/s or if you are planning to bump that up to 1066MT/s. If you are going to operate at the faster DDR speed than the layout of the interface and the power supply requirements for the memories needs review.
Regards, Bill

Jeff,

The software correctly checks for silicon revision and configures the core clocks and and DDR accordingly so other than replacing the silicon you also need to make sure software sets the clock to 600 Mhz.

Check board library code for evmK2G , pdk_am57xx_1_0_11\packages\ti\board\src\evmK2G\evmK2G.c. The following code needs to be updated and rebuilt so the PLL is set at 600 Mhz:

if(var == DEVSPEED1G)
{
ret = Board_PLLInit_1G();
}
else if(var == DEVSPEED600)
{
ret = Board_PLLInit();
}
else
return BOARD_UNSUPPORTED_FEATURE;

If you want to run the device at 600, you can remove all the if else code and hard code this to use default Board_PLLInit(); which configures the device to 600 Mhz configuration.

Similarly for DDR check the file pdk_am57xx_1_0_11\packages\ti\board\src\evmK2G\evmK2G_ddr.c.

if(var == DEVSPEED1G)
{
if (init_ddrphy(CSL_DDR_0_PHY_CFG_REGS, &ddr3phy_1066, 0) == false)
return BOARD_INIT_DDR_FAIL;
init_ddremif((CSL_Emif4fHandle)CSL_DDR3_0_SLV_CFG_REGS, &ddr3_1066);
}
else
{
if (init_ddrphy(CSL_DDR_0_PHY_CFG_REGS, &ddr3phy_800, 0) == false)
return BOARD_INIT_DDR_FAIL;
init_ddremif((CSL_Emif4fHandle)CSL_DDR3_0_SLV_CFG_REGS, &ddr3_800);
}

Remove the if else and only keep the code in the else that sets DDR to 800 MTs.

Regards,
Rahul

Hi Jeff,
If you followed those guidelines, you should be fine. I mentioned the DDR3L because we have had customers take some shortcuts on their DDR layout. DDR3L at 800MT/s may tolerate these short cuts but as the speed increases, the interface becomes less forgiving of layout defects.
Regards, Bill