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DM6437 DDR2 question

Anonymous
Anonymous

Hi All,

On page 14 of SPRS345d, DM6437 document, it is specified that the size of DDR2 memory space is only 256M.

We also see from the line above and below that another 768M and 1792M are reserved.

In addition to these, there are still many other reserved places in this memory-map table.

 

 

The question is: why DM6437 allow only 256MB of DDR2? The address is 32 bit, and 2^32=4GB, of which 256MB is only 1/16. And the total size of reserved address blocks adds up much more than 256MB. For example, 768M = 256M × 3 and 1792M = 256M × 7.

On a 32-bit Windows PC, the maximum memory is usually 2GB (not 4GB, since some address are reserved; my impression on this might be not exactly correct, but there is at least no problem for 32-bit XP machine to use 2GB DDR2), but 2GB is still 50% of the total logically possible 4GB memory space.

Why DM6437 only allocate 1/16 of the total memory space to DDR2l?


 

Regards,
Zheng

  • 0
    TI__Expert 8260 points

    Zheng,

    Where did u see DDR2 32-bit address bus for DM6437? There are only 13 address lines (DDR_A[0:12]). Look at page Page 42 in DM6437 data sheet (http://www.ti.com/lit/gpn/tms320dm6437). With 13-bit addess bus and 3 Bank Select Outputs (BA[2:0]), the DM6437 can support max 256MB DDR2 memory space, as mentioned in the data sheet memory map.

    The above math you did (2^no.of address lines) applies to linear memories. The same math doesn't apply to DDR2 memories. DDR2 meries use bank, row, column addresses.

    Consider the following example, where two 128MB DDR2 parts (that is 1Gbit memories) are connected to DM6437 (assume the same connections as in DM6437 EVM schematic, Page 14 (http://c6000.spectrumdigital.com/evmdm6437/reve/files/EVMDM6437_Schematic.pdf).

    Assume two 1Gb DDR2 parts: MT47H64M16 (8 Meg x 16 x 8 banks). As per the Addressing mentioned on Page 2 of MT47H64M16's data sheet (attached here for quick reference), BA[2:0] bits are used for Bank selection and address bits DDR_A[0:12] are used for row/column section. So, with 3-Bank select bits and 13-address bits, you can access (max) these two 16-bit 128MB memories (i.e. 128MB *2 = 256MB total).

    I hope this helps you to understand.

    Regards, Srirami.

  • Anonymous
    0 Anonymous in reply to srirami

    Dear Srirami,

    Thanks for the detailed answer. I am on travel right now, please allow me to study it some days later.

     

     

    Zheng

  • Anonymous
    0 Anonymous in reply to srirami

    Dear Srirami,

     

    Now I understand how address pins, row, column, bank and memory size are related. Thanks very much.

     

    But I still need to confirm one thing: For the 1Gbit 64M x 16 micron memory example you gave, since there are only 13 wires, does 13-bit row address and 10-bit column address needs to be send in two times?         

     

         

     

    Zheng

     

  • 0 in reply to Anonymous
    TI__Guru 64770 points

    Yes, they are transmitted in two different clock cycles.  This is a fundamental operation of synchronous DRAM type devices.  First a Row is activated during a RAS cycle and then specific Column addresses are used to access data, ie. CAS cycles.

  • Anonymous
    0 Anonymous in reply to BrandonAzbell

    Dear Brandon,

    I see it. Many thanks for this confirmation.

     

    Zheng