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AM5728: IPU/Bare Metal/System DMA and DDR3

Part Number: AM5728

Hello. I want to send a block of data(100 kiB)  from DDR3 to the fifo of uart. I have some questions:

1. Since I am using CCS, I think DDR3 is initialized by default. Am I right?

2. I did not understand the memory subsystem in AM5728. where is the code of the program written? in which memory(is that in IPU_RAM or IPU_ROM)? How much memory is there in AM5728? When we program different cores, for example M4 and A15, Where are these codes written?

3. How can we access DDR3? Can we write in that directly? what does EMIF do exactly? How can we be sure that nothing will be written in a part of DDR3 to avoid changing our data?

4. Is there any example(bare metal) for configuring system DMA? 

5. What is the difference of sending a packet and sending a block size(if the packet and block are equal in size)?

6. what will happen if I define a block size bigger than the fifo size of the uart?

7. Can I use OCM instead of DDR3 for testing DMA? If I can how? Where is the exact address of OCM? Can I write in that directly?

8. Can DDR3 generate a SDMA_request ?

Thanks a lot.

  • Ali,

    You seem new to our Sitara AM572x processor so thanks for considering this processor for your design. Let me start by providing some pointers to useful resources for you to locate information for the SOC.

    AM572x ti.com: http://www.ti.com/product/AM5728   (Technical reference manual, Datasheet and Errata)

    Useful resources: https://training.ti.com/am57x-sitara-processors-training-series 

    Software download: http://software-dl.ti.com/processor-sdk-rtos/esd/AM57X/latest/index_FDS.html 

    Questions:

    ali shayei said:

    Hello. I want to send a block of data(100 kiB)  from DDR3 to the fifo of uart. I have some questions:

    1. Since I am using CCS, I think DDR3 is initialized by default. Am I right?

    Using CCS doesn`t guarantee that DDR is initialized. You need to create a target configuration that links GEL initialization scripts on the A15, DSP and IPU and ensure that the console window when you connect to A15 (system master) shows clocks and DDR being initialization. If you are using one of TI evaluation hardware, you can follow the steps shown here:

    AM572x EVM: http://processors.wiki.ti.com/index.php/AM572x_GP_EVM_Hardware_Setup  

    AM572x IDK:http://processors.wiki.ti.com/index.php/TMDXIDK5728_Hardware_Setup

    If you build a custom platform, you would need to modify the script to match the clocking and the DDR part used on it using the SOC tools that we provide

    ali shayei said:
    2. I did not understand the memory subsystem in AM5728. where is the code of the program written? in which memory(is that in IPU_RAM or IPU_ROM)? How much memory is there in AM5728? When we program different cores, for example M4 and A15, Where are these codes written?

    AM572x is a hetrogeneous mutlicore device where each core has it own internal memory/cache and there is shared memory and external memory interfaces. Cortex M and Cortex A15 internal memory is usually all cached so the code typically executes from OCMC (Onchip L3 memory) or from external DDR memory that is connected to EMIF memory interface. The IPUSS includes a standard dual core Cortex M4 core with a wrapper of AMMU implmented to allow flexibility of remapping memory and access to different parts of the chip.

    This training on IPU core on AM57xx would be a good starting point for you:

    https://training.ti.com/running-rtos-on-arm-cortex-m4-processor 

    We have detailed the MEmory map for the chip in the Technical reference manual on ti.com: http://www.ti.com/product/AM5728 

    ali shayei said:
    8. Can DDR3 generate a SDMA_request ?

    No, DMA transfer requests can`t be generated by the DDR memory. This is not one of the interfaces that can generate a DMA interrupt event. Please check the interrupt controller section in the TRM to see what events can trigger a DMA transfer.

    Hope the information shared here helps you to get a starting point for your development. Please feel free to post further questions based on this information and we will try to provide the right guidance to keep your development going.

    Regards,

    Rahul