PROCESSOR-SDK-DRA7X: IPU MMU, GPIO5 access from CM4 code

Devendra T

Hi,

I have following query related to GPIO-5 access from cortex M4 code on DRA7xx (VAYU) board.

I am running Linux on CA15 and bare metal code on IPU. After connecting debugger to CA15, I am enabling all cores with the CCS gel script. CM4 MMU is configured by built in gel script.

I am allowing Linux to boot and then loading CM-4 binary with the help of debugger. From the bare metal code of CM4, when I try to access GPIO5 (0x4805B000), the CM4 core stops working. as per IPU MMU, this peripheral address lies in large page of 512 MiB. So I am not sure what is the issue here.

Awaiting your earliest response.

over 7 years ago

0 Nikhil Devshatwar over 7 years ago

TI__Genius 9905 points

Hi,

You need to make sure that Linux does not control GPIO5
Linux is smart, if nooone is using the GPIO5, it will turn the clock off.

So make sure that the GPIO5 is disabled in the Linux device tree so that it cannot mess up.
After that, M4 can freely use the GPIO5 registers at any point of time.

Regards,
Nikhil D

0 Devendra T over 7 years ago in reply to Nikhil Devshatwar

Intellectual 320 points

Nikhil,

Thanks for your reply. I forgot to mentioned above that, I have already disabled GPIO-5 in Linux device tree.

Regards,

Devendra

0 Nikhil Devshatwar over 7 years ago in reply to Devendra T

TI__Genius 9905 points

In that case, most likely the clocks are not turned on by the GEL file

Nikhil D

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PROCESSOR-SDK-DRA7X: IPU MMU, GPIO5 access from CM4 code