TMS320C6654: Clock LVDS Levels

Ramgopal Divakar

Part Number: TMS320C6654

Hello,

I plan to drive the 4 clock inputs to the C6654 (PCIe, core, SGMII, and DDR) from an IDT LVDS clock source. I don't see in the datasheet the clock swing levels. Can you point me where to look at and also confirm the table below matches the spec. Assume VDD is 3.3V in the table below. The DC offset is going to be removed by the AC coupling caps. I just want to make sure the AC swing is within spec.

over 7 years ago

0 Yordan Kovachev over 7 years ago

TI__Guru**** 161600 points

Hi,

Check Section 5.3 Recommended Operating Conditions (1) (2). After the table Note (1) and (2) state:
(1) All differential clock inputs comply with the LVDS Electrical Specification, IEEE 1596.3-1996 and all SERDES I/Os comply with the XAUI
Electrical Specification, IEEE 802.3ae-2002.
(2) All SERDES I/Os comply with the XAUI Electrical Specification, IEEE 802.3ae-2002

So the electrical characteristics of the differential clock inputs are described in LVDS Electrical Specification, IEEE 1596.3-1996.

If your clock source is compliant with the above mentioned spec (which it should be) and you follow the recommendations in Chapter 3 Clocking of the Hardware design guide (www.ti.com/.../sprabi2d.pdf ) your design should be ok.

Best Regards,
Yordan

0 Tom Johnson 16214 over 7 years ago in reply to Yordan Kovachev

TI__Mastermind 46460 points

Divakar,

The detailed clock specifications are contained in Section 5.7.4, Table 5-6 and Figures 5-5 and 5-6. Pay close attention to Figure 5-6. Unfortunately, I do not believe your clock source is compliant. The minimum differential level is 250mV p-p whereas your table has a minimum level of 247mV. You would also need to extrapolate the rise time in the middle 250mV. I believe this would be compliant to the rise time between 50ps and 250ps.

Tom

0 Ramgopal Divakar over 7 years ago in reply to Tom Johnson 16214

Expert 1335 points

Tom,

thank you. the IDT FAE wanted me to run it by you and now recommends HCSL since the picture you sent refers to PCIe which is normally HCSL. Below are the specs. Does this look okay?

0 Tom Johnson 16214 over 7 years ago in reply to Ramgopal Divakar

TI__Mastermind 46460 points

Divakar,

The LJCB input clock buffers are compatible with both LVDS and HCSL and LVPECL since the interface must be AC coupled. In this case, the signal is a little large. Since HCSL is a current output that must be properly biased to ground, the resistors can be selected to attenuate the signal to make it compliant. HCSL clock drivers normally have calculations for this. You can also refer to the Clocking Design Guide for KeyStone Devices Application Report (SPRABI4) for additional guidance.

Tom

0 Ramgopal Divakar over 7 years ago in reply to Tom Johnson 16214

Expert 1335 points

Tom,

regarding the IDT clock spec on LVDS above, the single ended swing minimum is 247. Differential is twice (Factory confirmed) so we are above the minimum of 250 mV or 494 mV. So we are compliant here. Now, the rise time (20% to 80%) is 300 ps or from 98.8mV to 395.2 mV. 50% of 254 mV you mention above is 127 mV which is 25% of 494 mV or it must be well within 300 ps to get here so we should be compliant here won't we?

Divakar

0 Ramgopal Divakar over 7 years ago in reply to Ramgopal Divakar

Expert 1335 points

On the rise and fall time:

IDT datasheet says 300 ps for 20% to 80% so minimum Vpp differential swing is is 494 mV and that gives a slew rate of 0.988 mv/ps. So for the 250 mV mentioned in the datasheet the rise time comes to around 253 mV. Which is within the 50-350 mentioned in the datasheet. Did I get it right?

0 Ramgopal Divakar over 7 years ago in reply to Ramgopal Divakar

Expert 1335 points

Typo. Meant 253 ps as the rise time.

0 Tom Johnson 16214 over 7 years ago in reply to Ramgopal Divakar

TI__Mastermind 46460 points

Divakar,

You missed my point that the signal was a little too large. The single-ended signal is 1150mv p-p. This will yield a 2300mv differential signal which is over the 2000mv max. The signal level will need to be attenuated through the resistors implemented on the output of the HCSL driver. This is commonly done and will yield a robust solution.

Tom

0 Ramgopal Divakar over 7 years ago in reply to Tom Johnson 16214

Expert 1335 points

Thanks Tom,
my last post was not concerning HCSL but LVDS.

Please refer to your response on

Apr 11, 2019 5:31 PM

Since the clock driver can be set for LVDS or HCSL, I am going back to the earlier post on LVDS where you had mentioned 247 mV was below the spec. 247 mV is single ended so differential swing is 494 mV min and tha max is 908 mV.

This is within spec in my opinion.

You also had a comment on the rise time.
I also think we are within spec in relation to the rise time.

If you are in agreement we can close this case.

0 Tom Johnson 16214 over 6 years ago in reply to Ramgopal Divakar

TI__Mastermind 46460 points

Divakar,

Are you sure that the 247mV is single ended? The Parameter description states "Differential Output Voltage for the TRUE Binary State". I read this as the differential voltage. Therefore, it is slightly too small. However, if the manufacturer assures you that this is a single-ended value and the the minimum differential voltage across the inputs will be greater than 250mV, then I agree that this is acceptable.

Tom

0 Ramgopal Divakar over 6 years ago in reply to Tom Johnson 16214

Expert 1335 points

Yes. We are pretty sure. Thanks for your time.

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TMS320C6654: Clock LVDS Levels