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AM3352: CPSW switch information

Sebastian Pfeiffer
Prodigy 70 points

Part Number: AM3352

Hi,

we will use the internal switch from the AM335x to connect (daisy chain) 30x products from us with the AM335x inside.

To clarify the requirement I need more information about the am335x switch and I have the following questions:

1.) switching capacity
2.) buffer size per port
3.) MAC buffer size
4.) store and forward / cut through switching 
5.) switching latency

Thanks in advanced!

regards,
Sebastian

  • 0
    TI__Mastermind 41230 points
    Hi,
    Here are the answers to the questions that are in the AM335x Technical Reference Manual (TRM)

    1.) switching capacity
    I am not sure I am following the question. If you are asking how many entries are in the ALE it is 1024. Each entry is a rule on how to forward the packet received or to be transmitted on a port based on MAC address in the packet. This section describes the ALE in the TRM 14.3.2.7 Address Lookup Engine (ALE).

    2.) buffer size per port
    Each port has a 20K FIFO that is balanced between RX and TX packets in the switch for store and foward between the ports. This is desribed in this section:
    14.3.2.7.2 Packet Forwarding Processes, the internal buffer sizes are described here 14.3.2.9 FIFO Memory Control.

    3.) MAC buffer size
    If I understand correctly the MAC buffer can be as large as you want it to be. The host port is connected to a DMA engine and as long as there are available RX descriptors packets will be received. Please be aware to look at the performance guide on the TI SDK User guides when designing your systems.
    14.3.2.4 CPDMA RX and TX Interfaces

    4.) & 5.) store and forward / cut through switching & switching latency
    14.3.2.15 Switch Latency
    The CPSW_3G is a store and forward switch. There is a table there that shows latency based on interface speed.

    Best Regards,
    Schuyler