Part Number: TMS320C6678
Hi,
I am working on a prototype board based on C6678 EVM board. I am able trying to do EDMA from DDR memory to Core 7 MSMC memory. When I try to perform EDMA3_DRV_requestChannel from core 7, it fails with the error 139 (EDMA3_DRV_E_INVALID_PARAM).
When I am trying to do the same for core 0, I am able to do so successfully.
I have gone through the example edma_test.c under the directory pdk_c667x_dspm2_2_0_6\packages\ti\csl\example\edma but could not find any clue. The initialization code (for all cores) is as given below.
#define NUM_EDMA3_INSTANCES 3
VOID EDMA3_Init (VOID)
{
EDMA3_DRV_Result EDMA_result = EDMA3_DRV_SOK;
EDMA3_RM_MiscParam miscParam;
UINT8 u8Instance;
/* Initialize all the EDMA3 Instances */
if(DNUM == CORE_0)
{
/* Configure it as master, if required */
miscParam.isSlave = FALSE; /* Core0 is MASTER */
for(u8Instance = 0; u8Instance < NUM_EDMA3_INSTANCES; u8Instance++)
{
EDMA_result = EDMA3_DRV_create(
u8Instance,
&(edma3GblCfgParams[u8Instance]),
(VOID *)&miscParam
);
if(EDMA_result != EDMA3_DRV_SOK)
{
OS_ASSERT(0);
return;
}
}
ghEdma[EDMA3_CC_INSTANCE_0] = EDMA3_InstanceInit(EDMA3_CC_INSTANCE_0);
if (NULL == ghEdma[EDMA3_CC_INSTANCE_0])
{
System_printf("EDMA instance 0 is not initialized");
OS_ASSERT(0);
}
ghEdma[EDMA3_CC_INSTANCE_1] = EDMA3_InstanceInit(EDMA3_CC_INSTANCE_1);
if (NULL == ghEdma[EDMA3_CC_INSTANCE_1])
{
System_printf("EDMA instance 1 is not initialized");
OS_ASSERT(0);
}
ghEdma[EDMA3_CC_INSTANCE_2] = EDMA3_InstanceInit(EDMA3_CC_INSTANCE_2);
if (NULL == ghEdma[EDMA3_CC_INSTANCE_2])
{
System_printf("EDMA instance 2 is not initialized");
OS_ASSERT(0);
}
}
System_printf("Core %d : EDMA instances initialized\n", DNUM);
/* Initializing EDMA in core-1 to core-7 alone*/
if( (DNUM >= CORE_1) && (DNUM <= CORE_7) )
{
ghEdma[EDMA3_CC_INSTANCE_0] = EDMA3_InstanceInit(EDMA3_CC_INSTANCE_0);
if (NULL == ghEdma[EDMA3_CC_INSTANCE_0])
{
System_printf("EDMA instance 0 is not initialized");
OS_ASSERT(0);
}
ghEdma[EDMA3_CC_INSTANCE_1] = EDMA3_InstanceInit(EDMA3_CC_INSTANCE_1);
if (NULL == ghEdma[EDMA3_CC_INSTANCE_1])
{
System_printf("EDMA instance 1 is not initialized");
OS_ASSERT(0);
}
ghEdma[EDMA3_CC_INSTANCE_2] = EDMA3_InstanceInit(EDMA3_CC_INSTANCE_2);
if (NULL == ghEdma[EDMA3_CC_INSTANCE_2])
{
System_printf("EDMA instance 2 is not initialized");
OS_ASSERT(0);
}
}
return;
} /* End of EDMA3_Init() */
EDMA3_DRV_Handle EDMA3_InstanceInit (UINT32 u32Edma3Id)
{
EDMA3_DRV_InitConfig initCfg;
Semaphore_Params semParams;
EDMA3_DRV_Result EDMA_Result = EDMA3_DRV_E_INVALID_PARAM;
EDMA3_DRV_Handle hEdma = NULL;
if (u32Edma3Id >= EDMA3_CC_INSTANCE_MAX)
{
return hEdma;
}
/* Save the Core ID to be used while registering the interrupts */
dsp_num = CSL_chipReadReg(CSL_CHIP_DNUM);
/* Save the Core ID to be used while registering the interrupts */
/**
* Driver Object created successfully.
* Create a semaphore now for driver instance.
*/
Semaphore_Params_init(&semParams);
initCfg.drvSemHandle = NULL;
EDMA_Result = edma3OsSemCreate(1, &semParams, &initCfg.drvSemHandle);
if (EDMA_Result == EDMA3_DRV_SOK)
{
/* Save the semaphore handle for future use */
semHandle[u32Edma3Id] = initCfg.drvSemHandle;
/* Driver instance specific config NULL */
initCfg.drvInstInitConfig = NULL;
initCfg.isMaster = TRUE;
/* Hook for running examples with default RM config */
/* configuration structure for the Driver */
initCfg.drvInstInitConfig = &stEDMA3_Inst_InitConfig[u32Edma3Id]\
[dsp_num];
/* Choose shadow region according to the DSP# */
initCfg.regionId = (EDMA3_RM_RegionId)dsp_num;
region_id = (EDMA3_RM_RegionId)dsp_num;
/*Saving the regionId for using it in the sample_cs.c file */
/* Driver instance specific config NULL */
initCfg.gblerrCb = NULL;
initCfg.gblerrData = NULL;
/* Open the Driver Instance */
hEdma = EDMA3_DRV_open (u32Edma3Id, (VOID *) &initCfg,&EDMA_Result);
}
if(hEdma && (EDMA_Result == EDMA3_DRV_SOK))
{
/**
* Register Interrupt Handlers for various interrupts
* like transfer completion interrupt, CC error
* interrupt, TC error interrupts etc, if required.
*/
registerEdma3Interrupts(u32Edma3Id);
}
OS_ASSERT(hEdma);
return hEdma;
} /* End of EDMA3_InstanceInit() */
When the EDMA initialization function EDMA3_Init(0 is executed for all the cores (0 to 7), it goes through successfully without any error.
The test function where the execution fails is given below:
struct EDMA3_ChannelParams
{
/*! The channel number to be returned to the fill the transfer params*/
UINT32 u32Ch;
/*! Handle for the instance ID*/
UINT8 hEdmaInst;
/*! CallBack function to be called after Transfer Completion */
EDMA3_RM_TccCallback TccCb;
/*! Pointer to data which will be passed directly
* to the TccCb CallBack function
*/
VOID *AppData;
};
struct EDMA3_ChannelParams stTest_DMA_ChParams;
EDMA3_DRV_Result edma3_test(VOID)
{
static UINT32 u32NumTimesEDMA_Test_Count = 0;
EDMA3_DRV_Result result = EDMA3_DRV_SOK;
EDMA3_DRV_Result EDMA_Result = EDMA3_DRV_SOK;
int i;
UINT32 acnt = A_CNT;
UINT32 bcnt = B_CNT;
UINT32 ccnt = C_CNT;
UINT32 count;
UINT32 Istestpassed = 0u;
INT32 Test_DMA_ChHandle = 0;
UINT32 u32EDMA3_Tcc = EDMA3_DRV_TCC_ANY;
for (count = 0u; count < (acnt*bcnt*ccnt); count++)
{
srcBuff1[count] = (INT8)count;
}
#ifdef EDMA3_ENABLE_DCACHE
System_printf("Core %d : Starting Flush\n",DNUM);
result = Edma3_CacheFlush((uint32_t)srcBuff1, (acnt*bcnt*ccnt));
System_printf("Core %d : Starting Invalidate\n",DNUM);
if (result == EDMA3_DRV_SOK)
{
result = Edma3_CacheInvalidate((uint32_t)dstBuff1, (acnt*bcnt*ccnt));
}
System_printf("Core %d : DONE CACHE Invalidate\n",DNUM);
if(result != EDMA3_DRV_SOK) OS_ASSERT(0);
#endif
stTest_DMA_ChParams.hEdmaInst = EDMA3_CC_INSTANCE_0;
stTest_DMA_ChParams.u32Ch = EDMA3_DMA_CHANNEL_ANY;
System_printf("Core %d : Opening DMA Channel\n",DNUM);
/* Requesting for first DMA Channel */
EDMA_Result = EDMA3_DRV_requestChannel(
hEdma, &(&stTest_DMA_ChParams)->u32Ch,
&u32EDMA3_Tcc,
(EDMA3_RM_EventQueue)0,
(&stTest_DMA_ChParams)->TccCb,
NULL
);
...
...
...
}
Kindly look into the above issue and provide input regarding the failure in EDMA3_DRV_requestChannel function for core 7.
Thanks,
Sridhar CR
