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CCS/AM5748: Unexpected debugging error of PCIe

rei
Mastermind 6155 points

Part Number: AM5748

Tool/software: Code Composer Studio

Hi,

My customers have checked the operation when accessing PCIe's Outbound area.
They are testing to disconnect the PCIe connection during communication assuming partner device trouble.

It has been checked now that accessing the outbound area while the PCIe connection is disconnected causes the CCS debugger to malfunction and stop working.

Test's description
Step1.Load the out file of PCIE_idkAM574x_wSoCFile_armExampleProject into A15_0 core.
Step2.Select RC using Teraterm.
Step3.Remove the PCIe connector during communication.
Step4. Access the outbound area that was connected
The following error is displayed in CCS at step 4

CortexA15_0: Trouble Halting Target CPU: (Error -1323 @ 0x80007568) Device failed to enter debug/halt mode because pipeline is stalled. Power-cycle the board. If error persists, confirm configuration and/or try more reliable JTAG settings (e.g. lower TCLK). (Emulation package 8.0.27.9)

Question1:
How does it usually work when accessing an outbound area that is disconnected?
(Customers think that CCS debugger has a problem.)

Question2:
They want to avoid debugging error and detect PCIe error in registers etc.
How can we detect errors?

■Environment
AM5748
CCS v8.1.0
HW TMDSIDK574
SW pdk_am57xx_1_0_11
Sample:PCIE_idkAM574x_wSoCFile_armExampleProject

Regards,
Rei

  • 0
    TI__Guru* 95265 points
    Hi,

    Q1. The PCIE outbound region is address 0x2000_0000 (for PCIE SS1) it mapped to the memory of the other end. When you use CCS memory window to look at this address, it is the content of the other side. If you disconnect the PCIE connection, the PCIE will hang. This is not a bug, it is common behavior when you looking into a mapped region that is not available.

    Q2. There are many PCIE error status registers, but I am not aware any of them is dedicated to detect PCIE disconnected. The disconnection caused the link down, you may look at the PCIECTRL_TI_CONF_DEVICE_CMD, bit 1:5 LTSSM_STATE for this purpose.

    Regards, Eric