AM5716: EMIF access

Masashi,

The DDR EMIF provides support for up to 2GB of memory.  This is all available on CS0.  The L3 memory map provides access to all 2GB through addressing in 2 blocks Q2 and Q3.  The first half of the SDRAM is accessible at 0x8000_0000 to 0xBFFF_FFFF and the second half is accessible at 0xC000_0000 to 0xFFFF_FFFF.  The SDRAM can be accessed by any system master through the L3 at these addresses.  This is explained in Section 2.2 and Table 2-1 of the TRM.

The MPU has an MMU that allows it an address map that extends beyond 32 address bits.  Blocks Q2 and Q3 are then shown again in Section 2.4 and Table 2-8 for the MPU address map.  These are accesses mapped through the L3.  Then using the MMU associated with the MPU core, the first half of the SDRAM is accessible at 0x2_0000_0000 to 0x2_3FFF_FFFF as block Q8.  All of the SDRAM is then accessible again at 0x2_8000_0000 to 0x2_BFFF_FFFF and 0x2_C000_0000 to 0x2_FFFF_FFFF, as blocks Q10 and Q11, respectively.  Accesses at blocks Q8, Q10 and Q11 all use the MMU associated with the MPU core and they bypass the L3.

Q8 and Q10 are aliased copies of the first half of the SDRAM accessible through Q2.  Similarly, Q11 is an aliased copy of Q3.  However, accessing the same physical memory locations at different aliased memory addresses is not allowed if coherency is needed.

Tom