AM6548: DDR3 trace impedance

Zoran,

Where do you see in SPRAC76C that the DDR routes are to be 39 ohms SE and 78 ohms DIFFE?  Although lower trace impedances can be implemented for DDR  routes, the increased dielectric thickness and wider trace width and spacing make this more challenging - especially when trying to keep the board cost at a minimum.  This is why we provide routing guidance for a nominal 50-ohm layout.

Note that the impedance range in row PS9 of Table 1 provides a minimum impedance of 40 ohms and then the next row, PS10, provides the tolerance for this value.  39 ohms is essentially the same and within this impedance margin.

Tom

Tom,

Thanks a lot for your reply. Please take a look at the table "Impedance Constraints Information I" in the SPRAC76C (page 27). For  example impedance #6. This is Surface microstrip (Top layer) with 8.2 mil line width. Target impedance is 40 Ohms. Now, please note the impedance #8 which is stripline at Layer L03_Sig1 with 5 mil width and, again, 40 Ohms target impedance. Now, take a look at any of the DDR address lines on the IDK pcb. All single ended traces routed over Top layer and Layer L03_Sig1 are routed with a traces of 8.2 mill on Top layer and 5 mils on L03_Sig1. Moreover, if you take a look at the Constraints (Allegro Constraints Manager)  you will find that there are two Physical constraint sets named DDR_40E and DIFF_80E. All DDR nets have DDR_40E as referenced Physical CSet and all differential DDR nets have DIFF_80E as Referenced CSet. This means that all single ended DDR nets are routed with 40 Ohms impedance traces and all differential DDR nets are routed with 80 Ohms differential traces. As I previously mentioned, on the IDK schematic 39.2 Ohms termination resistors are used.

Maybe I overlooked something?

Regards,

Zoran

Zoran,

What additional information do you want?

Tom