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TCI6630K2L: Endianness configuration on C66x cores

Robert Dupuit
Prodigy 20 points

Other Parts Discussed in Thread: TCI6630K2L, TI-CGT

Hi,

I am working on a TCI6630K2L device, and am struggling with its endianness configuration. I am trying to configure the whole chip in Big-endian, so I did what is described in the K2L data sheet (SPRS893E) and set the Lendian pin to a low-level (pull-down).

Regarding the ARM side, the cores start nevertheless in Little-endian but can be then switch to Big-endian by Software (I am fine with that). Moreover the Big-endian configuration is automatically inherited in the AXI2VBUS bridge at startup (no action from software is required) for every of the ARM cores.

However the C66x cores seem to be in a undocumented hybrid endianness where they are expecting instructions encoded in Little-endian, but are performing every memory accesses in Big-endian (same as for the ARM cores, but this is the documented / expected behaviour). The bit EN of CSR register is cleared, telling that the cores are in Big-endian. My issue is that the TI-CGT-C6000 toolchain (I am using version 8.1.3) cannot generate object code that match the behaviour of the C66x cores in Big-endian: object code are either in Little-endian or in Big-endian (including the instructions).

Am I missing something on either sides (Keystone II chip or toolchain) ?

Regards,

Robert

  • 0
    TI__Guru* 85315 points

    I am going to have my colleague double-check this - but I expect all of our devices here to support little endian only. 

    If there is any big endian configuration references, that is typically not supported by our software and compilers AFAIK and is likely just documented but not supported. 

    Regards

    Mukul 

  • 0
    TI__Guru** 116830 points

    Robert,

    For SOC system endian setting (DSP And interconnect), setting the LE pin should be sufficient. Can you confirm when you connect to the C66x using CCS after setting up the LE pin to big endian that the DSP is detecting the system endian correctly. Check bottom right of the IDE window and you should see a BE reference on the system mode detected by the emulation driver. I am assuming that during code generation, that you have changed the compiler settings to generate big endian code.

    As Mukul indicated, TI software is deprecating support for big endian due to lack of many use cases and to avoid the duplication of validation effort with little and big endian binaries for our software teams. TI RTOS has already dropped support for big endian for DSP in newer releases so we will need to confirm with the compiler team that the compiler version that you are using does support the big endian mode. 

    Regards,

    Rahul 

  • 0 in reply to Rahul Prabhu
    Prodigy 20 points

    Mukul, Rahul,

    Thanks for getting back to me.

    I am not using CSS so I cannot do what you are asking me, but since I am observing several registers that correctly reflect the state of the Lendian pin, I guess CSS would report that the platform is in Big-endian.

    Regarding the toolchain, I added the --big_endian flag in compilation flow and as I described, this option also changes the instruction encoding to Big-endian. However the C66x cores seem to expect Little-endian encoded instructions regardless of the Lendian pin configuration.

    I fully understand TI choice to drop the Big-endian support, but I would just like to be sure that my analysis is correct, and if a version (branch or deprecated) of the TI-CGT toolchain that supports the C66x big-endian behaviour of Keystone II chip happen to exist.

    Regards,

    Robert

  • 0 in reply to Robert Dupuit
    TI__Guru** 116830 points

    Robert,

    Any version of TI CGT 7.x will support big endian mode for the DSP.  You can download that from link below. 

    http://www.ti.com/tool/download/C6000-CGT-7-4

    For Big endian support in software you will need to use the processor sDK baseline from 2018 which is the last baseline with big endian support on these devices.

    Regards,

    Rahul