Part Number: TMS320C6748
I use the DSPF_sp_fftSPxSP_674_LE_ELF project TI provided for test.
The project directory is ..\ti\dsplib_c674x_3_4_0_0\packages\ti\dsplib\src\DSPF_sp_fftSPxSP\c674\DSPF_sp_fftSPxSP_674_LE_ELF
In the project, the default "MAXN" is 256, N = FFT length. And the project does not enable Cache.
I use following lines to enable Cache:
CacheEnableMAR((unsigned int)0xC0000000, (unsigned int)0x10000000);
CacheEnableMAR((unsigned int)0x80000000, (unsigned int)0x20000);
CacheEnable(L1DCFG_L1DMODE_32K | L1PCFG_L1PMODE_32K | L2CFG_L2MODE_256K);
I find that:
1、 When N<=256, the program runs right with or without Cache enabled.
2、 When N>=1024, the program runs right with Cache disabled.
3、 When N>=1024, the program runs right with L1P and L1D Cache enabled.
4、 When N>=1024, the program runs wrong with L1P and L1D and L2 Cache enabled. The program run out. Some times, it has error: "C674X_0: Trouble Reading Memory Block at 0xc00178dc......."
The nature C version of the fftSPxSP has no problem. The assembly version of the fftSPxSP has the problem.
The program is attached below.
Can you help me why the the assembly version of the fftSPxSP can not work normally with L2 Cache enabled?
Because for the efficiency, I have to use L2 Cache, and I have to use fftSPxSP with N>=1024.
Thank you.DSPF_sp_fftSPxSP.zip