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TDA4VM: Main domain R5 core RAM performance issue

Part Number: TDA4VM
Other Parts Discussed in Thread: SYSBIOS

Dear experts:

I did some RAM speed tests on both A72 core and R5 core, A72 runs Linux and R5 runs sysbios. RAM performance seems fine on A72 core, but I got a bad speed result on R5 core.

The table below is the R5 core RAM speed result, each test do a 16MB data processing

I wonder if these result is correct. If yes, then could you give me some advice to optimise it? Or is R5 core RAM performance totally fixed to this?

Thanks

  • Hi 

    We will follow up internally on the data measured. Can you please share more details if you are using standard C functions for the measurement? Where is the code executing from? Are you ensuring you have the right compiler flags to optimize the code for speed?

    Thanks and Regards

    Piyali

  • Hi Piyali,

    My test code is simple:

    int test_copy_size = 0x1000000;
    
    void *cache_src = (void *)0x81000000;
    void *cache_dst = (void *)0x82000000;
    void *noncache_src = (void *)0xa5000000;
    void *noncache_dst = (void *)0xa6000000;
    
    Types_FreqHz freq;
    Types_Timestamp64 t64, tt64;
    
    Timestamp_getFreq(&freq);
    
    Timestamp_get64(&t64);
    memset(cache_src, 0xa5, test_copy_size);
    Timestamp_get64(&tt64);
    
    CpswAppUtils_print("--- time64: %lu %09lu\n", (t64.hi << 2) + t64.lo / freq.lo, t64.lo % freq.lo);
    CpswAppUtils_print("--- time64: %lu %09lu\n", (tt64.hi << 2) + tt64.lo / freq.lo, tt64.lo % freq.lo);
    

    Repeat memset() and memcpy() with different address areas.

    I load the binary through CCS, so there is only one R5 core running, other cores remain halted.

    And here is the R5 core MPU settings:

    I think the compiler flags is right, since the instructions in disassembly seem no problem. R5 core is busy looping in the pictures below

    memset:

    memcpy:

    Thanks for your confirmation.

  • Thanks! Couple of follow up questions:

    1. What is the caching policy you are using for the cached data? WB, WA, WT, Strongly ordered, Device memory?

    2. What is the DDR frequency at which you are operating at? 3733 MT/s?

    3. Can you please make sure the R5F is running at 1 GHz?

    Thanks and Regards

    Piyali

  • Hi Piyali,

    I got some confirmation from my local FAE, that R5 core has no optimisation on DDR throughput, maybe next generation SoC will boost DDR performance.

    Thanks for your help, I will mark this issue as resolved.