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PROCESSOR-SDK-K2L: TCI6630K2L FFTC Accelerator, CP addition limitations for some DFT sizes

Krishna Madhuri Mandalapu
Prodigy 20 points

Part Number: PROCESSOR-SDK-K2L
Other Parts Discussed in Thread: TCI6630K2L

Hi,

I am working on FFTC Accelerator(K2L platform). I observed that for DFT sizes 1024, 512, 256, 128 CP addition is happening in the beginning(.i.e,. CP followed by symbol. Lets take CP as 4 then last 4 samples will be added in the beginning). For 64, 32 and 16 DFT sizes CP addition is happening at the end(.i.e., Symbol followed by CP. Lets take CP as 4 then first 4 samples will be added in the last). And for DFT size 8 some junk IQ's are coming as CP. 

All these DFT sizes are supported by FFTC accelerator according to K2L Data Sheet. DFT output is correct but CP position and values are going wrong.

Now my question is why the behavior of FFTC accelerator is so? Is there any mistake in configuration or the accelerator it self acts that way or Is there any other way of configuring for DFT sizes 64, 32, 16 and 8 so that CP addition happens in the beginning?

Here are the Configurations:

pFFTTestCfg->fftcQCfg.controlRegConfig.dftSize                      =   128;

pFFTTestCfg->numBlocks                                              =   1;

pFFTTestCfg->fftcQCfg.cyclicPrefixRegConfig.bCyclicPrefixAddEnable = 1;

pFFTTestCfg->fftcQCfg.cyclicPrefixRegConfig.cyclicPrefixAddNum = 4;

pFFTTestCfg->fftcQCfg.controlRegConfig.bSupressSideInfo             =   0;

pFFTTestCfg->fftcQCfg.scalingShiftingRegConfig.bDynamicScaleEnable = 1;
pFFTTestCfg->fftcQCfg.scalingShiftingRegConfig.radixScalingValLast = 0;
pFFTTestCfg->fftcQCfg.scalingShiftingRegConfig.radixScalingVal[0] = 0;
pFFTTestCfg->fftcQCfg.scalingShiftingRegConfig.radixScalingVal[1] = 0;
pFFTTestCfg->fftcQCfg.scalingShiftingRegConfig.radixScalingVal[2] = 0;
pFFTTestCfg->fftcQCfg.scalingShiftingRegConfig.radixScalingVal[3] = 0;
pFFTTestCfg->fftcQCfg.scalingShiftingRegConfig.radixScalingVal[4] = 0;
pFFTTestCfg->fftcQCfg.scalingShiftingRegConfig.radixScalingVal[5] = 0;
pFFTTestCfg->fftcQCfg.scalingShiftingRegConfig.radixScalingVal[6] = 0;

pFFTTestCfg->fftcQCfg.controlRegConfig.dftMode                    =   Fftc_DFTMode_IDFT;

pFFTTestCfg->fftcQCfg.destQRegConfig.bInputFFTShift = 0;
pFFTTestCfg->fftcQCfg.destQRegConfig.inputShiftVal = 0;

Thanks and Regards,

M Krishna Madhuri