66AK2G12: Working with interrupts using ARM core and OSAL HwiP library

Krishna Boopathy J

Intellectual 340 points

Part Number: 66AK2G12

Hi Team,

I have been running TI-RTOS on ARM core of the 66AK2G12 processor.

I am using the HwiP library to take care of interrupts found in <ti\pdk_k2g_1_0_14\packages\ti\osal\> location.

I am using the following code to test my TIMER1 interrupt.

#define TIMER1_EVTID 51

int var=0;

void gic_init()
{
    HwiP_Handle hwi0;
    HwiP_Params hwiParams;

    HwiP_Params_init(&hwiParams);
    
    hwi0 = HwiP_create(TIMER1_EVTID, myISR, &hwiParams);
    HwiP_enableInterrupt(TIMER1_EVTID);

}

void myISR()
{

    var=1;

}

inside the main task loop()
{
    gic_init();
    while(1)
    {
        if(var==1)
            UART_printf("\n INTERRUPT OCCURED");
    }
}

I have enabled the timer interrupt in the TIMER1_INTCTL_STAT register too.
When the timer overflows I can see the interrupt getting triggered in the TIMER1_INTCTL_STAT register.

But the HwiP interrupt is not getting triggered.

Do let me know if I am missing out anything.?

With Thanks,
Krishna.

over 5 years ago

0 Rahul Prabhu over 5 years ago

TI__Guru** 116170 points

Krishna,

Please refer to the OSAL test for K2G that is provided in the directory below:

pdk_k2g_1_0_xx\packages\ti\osal\test\src

In the source file, if you search for K2G, you will see that Time ID 1 has been used in this setup so you should be able to reference the test to check the timer1 setup.

Please review the code and let us know if it helps.

Regards,

Rahul

0 Krishna Boopathy J over 5 years ago in reply to Rahul Prabhu

Intellectual 340 points

Hi Rahul,

We are using a custom Timer library and we are utilising only the ARM core.

I am using the following code for setting up the interrupt.

void gic_init()
{

HwiP_Handle hwi0;
HwiP_Params hwiParams;

HwiP_Params_init(&hwiParams);
hwiParams.evtId = TIMER1_EVTID;
hwi0 = HwiP_create(1, myISR, &hwiParams);
HwiP_enableInterrupt(1);

}

For the Event ID, I tried with both 51 [GIC-400ID] and 19[SPI Event No.]. Interrupt not getting generated for both.

I referred to the example code. Please do let me know if I have to do anything differently. If I post the interrupt using HwiP_post(TIMER1_EVTID);, the interrupt is occurring fine with no issues.

I have also checked with the "TIMER_INTCTL_STAT" register. After the timer overflows the bit "PRDINTSTAT_HI" is getting set and "PRDINTEN_HI" is also in high state.

So is there any further configuration needed to be done with the ARM Interrupt controller.

Thanks.

With Regards,
Krishna.

0 Krishna Boopathy J over 5 years ago in reply to Krishna Boopathy J

Intellectual 340 points

Hi Rahul,

Kindly treat this as a gentle reminder. Is there an update for this issue.?

With Thanks,
Krishna

0 Krishna Boopathy J over 5 years ago in reply to Krishna Boopathy J

Intellectual 340 points

Hi Rahul,

We are again facing a similar issue with DMA interrupts.

Again after completion of DMA, I can see the interrupt getting set in the EDMAA_IPR interrupt pending register.

But the functions that I register with EDMA Event ID using HwiP_create is not getting invoked.

For both Timer and DMA utilities, we are using our own custom drivers because directly manipulating registers to setup EDMA took us minimum time which is our requirement.

So kindly let me know any workaround or any example code to use Hwi_create functionality, to setup and register ISR with hardware interrupts for the ARM core in the K2G processor.

With Regards,

Krishna.

0 lding over 5 years ago in reply to Krishna Boopathy J

TI__Guru* 95265 points

Hi,
In the code:
HwiP_Handle hwi0; 
HwiP_Params hwiParams; 
HwiP_Params_init(&hwiParams); 
hwiParams.evtId = TIMER1_EVTID; 
hwi0 = HwiP_create(1, myISR, &hwiParams); 
HwiP_enableInterrupt(1);
Inside HwiP_create(), intNum = 1 seems doesn't right. Please use EDMA or timer1 SPI event number + 32 (see K2G TRM Table 6-2. AINTC Interrupt Sources). 
Also, inside hwiParams, there is a field called triggerSensitivity
typedef enum
{
/**< Corresponding interrupt is level-sensitive */
 OSAL_ARM_GIC_TRIG_TYPE_LEVEL = 1,
/**< Corresponding interrupt is edge */
 OSAL_ARM_GIC_TRIG_TYPE_EDGE = 2,
/**< Coressponding interrupt is high level sensitive */
 OSAL_ARM_GIC_TRIG_TYPE_HIGH_LEVEL = 3,
/**< Coressponding interrupt is low level sensitive */
 OSAL_ARM_GIC_TRIG_TYPE_LOW_LEVEL = 4,
/**< Coressponding interrupt is rising edge sensitive */
 OSAL_ARM_GIC_TRIG_TYPE_RISING_EDGE = 5,
/**< Coressponding interrupt is falling edge sensitive */
 OSAL_ARM_GIC_TRIG_TYPE_FALLING_EDGE = 6
} OSAL_armGicTrigType_t;
Please try using 1 or 2 to see if it helps.
Regards, Eric

0 Krishna Boopathy J over 5 years ago in reply to lding

Intellectual 340 points

Hi Eric,

lding said:
Inside HwiP_create(), intNum = 1 seems doesn't right. Please use EDMA or timer1 SPI event number + 32 (see K2G TRM Table 6-2. AINTC Interrupt Sources).

Yes we have already rectified this after referring to the example codes provided.

lding said:
Also, inside hwiParams, there is a field called triggerSensitivity

But this is what was causing the issue. Initializing this parameter to OSAL_ARM_GIC_TRIG_TYPE_LEVEL (or) OSAL_ARM_GIC_TRIG_TYPE_RISING_EDGE (or) OSAL_ARM_GIC_TRIG_TYPE_FALLING_EDGE didn't work and ISR function was never invoked even though interrupt flag was set.

But changing the parameter "OSAL_ARM_GIC_TRIG_TYPE_EDGE" did the trick.
Tested the changes with DMA interrupt and ISR was triggering fine without any issues.

Thanks for the support.

Regards,
Krishna

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66AK2G12: Working with interrupts using ARM core and OSAL HwiP library