Compiler/DRA746: gcc

Kevin Chen36

Part Number: DRA746

Tool/software: TI C/C++ Compiler

Hi,

I need to configure some pins like vout1.d9 pad etc. as GPIO mode with input and internal pull dowm in dts. However, the dts seems not to have example code. Can you provide an example code for me? Thank you!

Best regards

Kevin

over 5 years ago

0 Keerthy J over 5 years ago

TI__Guru**** 168820 points

Hi Kevin,

The whole pin muxing is done in the u-boot for DRA7.

File: board/ti/dra7xx/mux_data.h

Your requirement can be done as per below. Pad vout1.d9 mux mode 14 corresponds to gpio8_9.

Also as per your question it is in internal pull down.
Doc: http://www.ti.com/lit/ds/symlink/dra746.pdf page: 76

diff --git a/board/ti/dra7xx/mux_data.h b/board/ti/dra7xx/mux_data.h
index 75da5cb608..dceb51b217 100644
--- a/board/ti/dra7xx/mux_data.h
+++ b/board/ti/dra7xx/mux_data.h
@@ -86,7 +86,7 @@ const struct pad_conf_entry dra72x_core_padconf_array_common[] = {
        {VOUT1_D6, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d6.vout1_d6 */
        {VOUT1_D7, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d7.vout1_d7 */
        {VOUT1_D8, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d8.vout1_d8 */
-       {VOUT1_D9, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d9.vout1_d9 */
+       {VOUT1_D9, (M14 | PIN_INPUT_PULLDOWN)}, /* vout1_d9.gpio8_9 */
        {VOUT1_D10, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d10.vout1_d10 */
        {VOUT1_D11, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d11.vout1_d11 */
        {VOUT1_D12, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d12.vout1_d12 */

0 Kevin Chen36 over 5 years ago in reply to Keerthy J

Intellectual 400 points

Hi Keerthy,

Thank you for your response. I did modified board/ti/dra7xx/mux_data.h and all gpio pins were in pull dowm satate (0V) when EVM entered in u-boot. So these gpio pins do not have expected result after EVM entering kernel mode. Especially the gpio8_9 always is high (3.3V) until I execute "echo 233 > /sys/class/gpio/export" command. Have you any ideas for EVM entering kernel mode? Thank you!

Best regards

Kevin

0 Keerthy J over 5 years ago in reply to Kevin Chen36

TI__Guru**** 168820 points

Hi Kevin,

Which means as soon as you put the pad to gpio mode in kernel it is getting back
to expected value.

Could you please get me the value of the pad config register in the kernel:

devmem2 0x4a003600

If there is mode change compared to u-boot. We can suspect what might be happening.

Also at u-boot can you get me the value of the the same register:

md 0x4a0036000

Regards,
Keerthy

0 Kevin Chen36 over 5 years ago in reply to Keerthy J

Intellectual 400 points

Hi Keerty,

My expection for getting back is low (0V) but gpio8_9 is always high.. Below is my measured result, FYR!

Kernel:

Memory mapped at address 0xb6fed000.
Read at address 0x4A003600 (0xb6fed600): 0x0004000E

U-boot:

U-Boot# md 4a003600
4a003600: 0004000e 0005000e 0004000e 0005000e    ................
4a003610: 0004000e 0004000e 0005000e 0005000e    ................
4a003620: 0005000e 0005000e 0005000e 0005000e    ................
4a003630: 0005000e 0005000e 0005000e 0001000e    ................
4a003640: 0005000e 0005000e 0005000e 0005000e    ................
4a003650: 00040100 00040100 00040100 00040100    ................
4a003660: 00040100 00040100 00040100 00040100    ................
4a003670: 00040100 00040100 00040100 00040100    ................
4a003680: 0005000e 0001000e 0005000e 0005000e    ................
4a003690: 0005000e 0005000e 0005000e 0005000e    ................
4a0036a0: 0005000e 0005000e 0005000e 0005000e    ................
4a0036b0: 0005000e 0005000e 0005000e 0005000e    ................
4a0036c0: 0005000e 0005000e 0005000e 0005000e    ................
4a0036d0: 0005000e 0005000e 0005000e 0005000e    ................
4a0036e0: 0005000e 0005000e 0005000e 0005000e    ................
4a0036f0: 0005000e 0005000e 0005000e 0005000e    ................

Best regards

Kevin

0 Keerthy J over 5 years ago in reply to Kevin Chen36

TI__Guru**** 168820 points

Hi Kevin,

So there is no change in the pad register between u-boot and kernel.
You are seeing that u-boot the level of this GPIO is low and kernel it
automatically becomes high? What is your expectation at kernel level?

In kernel you can set the gpio level to low by doing a simple gpio-hog.

p1 {
gpio-hog;
gpios = <9 GPIO_ACTIVE_HIGH>;
output-low;
line-name = "gpio8_9";
};

The above node can be added inside gpio8 node in the dts dra7-evm.dts

- Keerthy

0 Kevin Chen36 over 5 years ago in reply to Keerthy J

Intellectual 400 points

Hi Keerthy,

Thank you for your quickly response for my question.

We did add inside gpio8 node in the dts dra7-evm.dts and the gpio8_9 is low (0V). But I hope the direction of gpio8_9 is input and pull down. We do not why it always is high in kernel mode........

Best regards

Kevin

0 Keerthy J over 5 years ago in reply to Kevin Chen36

TI__Guru**** 168820 points

Kevin,

If we check:

The value you read confirms that: 0x0004000E

CTRL_CORE_PAD_VOUT1_D9 register:

Bit 18: VOUT1_D9_INPUTENABLE is set Receive mode is enabled so INPUT
Bit:17 VOUT1_D9_PULLTYPESELECT 0x0: Pull Down is selected
Bit 3:0 VOUT1_D9_MUXMODE: 14 is 0xE: gpio8_9.

This takes care of the PAD layer.

gpio-hog pulls it low from the GPIO layer.

Hope it clarifies?

- Keerthy

0 Kevin Chen36 over 5 years ago in reply to Keerthy J

Intellectual 400 points

Hi Keerthy,

Does the meaning of "PAD Layer" need to check PCB?

Best regards

Kevin

0 Keerthy J over 5 years ago in reply to Kevin Chen36

TI__Guru**** 168820 points

Kevin,

1) Can you confirm the state of GPIO8_9 is always high in u-boot & kernel without the gpio-hog or the export?
If after setting the register 0x4a003600 to 0x0004000e you are seeing a high value then there has to be an external pull.
Only that can explain.

2) I did not understand "Does the meaning of "PAD Layer" need to check PCB?" Can you please elaborate.

- Keerthy

0 Kevin Chen36 over 5 years ago in reply to Keerthy J

Intellectual 400 points

Hi Keerthy,

Please see my answers inline below. Thank you!

1) Can you confirm the state of GPIO8_9 is always high in u-boot & kernel without the gpio-hog or the export?
If after setting the register 0x4a003600 to 0x0004000e you are seeing a high value then there has to be an external pull.
Only that can explain.

[Kevin] The GPIO8_9 is low in u-boot but it become high in kernel without the gpio-hog or the export.

2) I did not understand "Does the meaning of "PAD Layer" need to check PCB?" Can you please elaborate.

[Kevin] I do not understand what the "PAD Layer" is you mentioned in your previous response. I guess your meaning is I need to check if external pull high design in our schematic.

Best regards

Kevin

0 Keerthy J over 5 years ago in reply to Kevin Chen36

TI__Guru**** 168820 points

Kevin,

Thanks. Are you looking at the signal using an oscilloscope?

So at u-boot when the register reads 0x4000E you see it low but on kernel if you are seeing
it high even when it the register reads 0x4000E(without gpio-hog or export). Then the only possible
explanation is an external source is pulling it high in kernel. as 0x4000E for vout1.D9 pad means input
pull down and in GPIO8_9 mode.

If you can confirm that in kernel the register reads 0x4000E when it is high(without gpio-hog or export)
then it should be due to an external pull.

I hope this is the information needed. If you no other questions can you resolve this thread?

- Keerthy

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