Hi
I would like to reset one core from another core.
In case of one core crush.
1. Can i reset one core from another core ?
2. if yes how ?
3. will the reset damage global resource of the DSP like serial port, network?
Thank You
Doron Gabbay
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Hi
I would like to reset one core from another core.
In case of one core crush.
1. Can i reset one core from another core ?
2. if yes how ?
3. will the reset damage global resource of the DSP like serial port, network?
Thank You
Doron Gabbay
Hi,
Yes, it is possible. Please see the datasheet https://www.ti.com/lit/ds/symlink/tms320c6678.pdf. Section 7.5, Reset Controller, then CPU local reset.
Regards, Eric
Hi
But local reset as said in section 2.2.3 at sprugv4c power slip controller pdf
Is intended for watchdog timer and we would like to use it when no watchdog is activated.
Doron Gabbay
Hi,
Local reset can be done in several ways: if you don't have WD, there is also "• LPSC MMRs (memory-mapped registers) " for this purpose.
Regards, Eric
Hi Eric
How do i debug that i did the reset properly and core that was reset did reset.
Doron Gabbay
Hi,
If a core is in local reset, you can't connect it with CCS/JTAG.
Regards, Eric
Hi Dear Eric
Will other cores be able to connect?
if core 0 reset on core 1 how do we know that core 0 is still continue to function without resetting itself.
Regards
Doron Gabbay
Hi,
All other cores are not in local reset can run normally and can be connected by JTAG.
>>>>if core 0 reset on core 1 how do we know that core 0 is still continue to function without resetting itself.>>>>It runs normally, it is same way how you know a core is running. Maybe you can print something, toggle a GPIO ... you can also connect with JTAG to see where the program is.
Regards, Eric
Hi Eric
Can we initiate a software local reset
To one of the cores as mentioned above ?
Since section 7.5 is about pin configurable local reset.
Regards
Doron Gabbay
Hi,
7.5.4 Local Reset:
• LPSC MMRs (memory-mapped registers)
Yes, you can use software to do a local reset via LPSC domain registers.
Regards, Eric
Hi Eric
On section 7.5.4 there is no much information on
How to do a software local reset on a specific core from another core.
On table Table 7-9 last row
MMR bit in LPSC controls C66x CorePac local reset. Used by watchdog timers.
does it mean that the LPSC register will be used in the WD and not accessible as you wrote for software local reset.?
It would be best if you can provide software example for software core reset initiated by other cores.
Regards
Doron Gabbay