TDA2P-ACD: Vout_1 Spread Spectrum

Behnam Eskandariun1

Part Number: TDA2P-ACD

Hi,

Since we are facing some issues in EMC in the RGB clock freq range, I was wondering if spread spectrum feature is available on Vout1_clk output. I've been checking the TRM (SPRUIF0C–May 2017–Revised February 2020) to figure it out. It seems there is an Spread spectrum feature available but it's not supported for this output! Could you please support me by answering following questions?

- Is the Spread Spectrum supported on Vout1_clk output?

- If yes, How we can enable the spread spectrum feature?

Thank you very much.

Behnam

over 5 years ago

0 kcastille over 5 years ago

TI__Guru 56317 points

Benham,

You can reference this appnote to enable spread spectrum on the VOUT interfaces:

Jacinto6 Spread Spectrum Clocking Configuration (Rev. A)

Regards,

Kyle

0 Behnam Eskandariun1 over 5 years ago in reply to kcastille

Prodigy 90 points

Hello Kyle,

We have observed following info in the TRM. What does it mean "The SSC feature is not supported"?

Regards,

Behnam

0 Alexander Quinones over 5 years ago in reply to Behnam Eskandariun1

Intellectual 310 points

Hi Kyle

in the referred app note there is a reference to a excel file, but the link to it is not correctly indicated:

May you please provide the correct URL?

Thanks,

Alexander

0 kcastille over 5 years ago in reply to Alexander Quinones

TI__Guru 56317 points

Alex,

I've attached the xls.

Regards,

KyleJacinto6_ADPLLs_SSC_config.xlsm

0 Alexander Quinones over 5 years ago in reply to kcastille

Intellectual 310 points

Hi kcastille

Thanks a lot for the excel file.

Now the only thing left open is if the TDA2P-ACD support SSC in Vout_1 pad, since the App Note seems to imply that (but is written for several TDAx SoCs) but the TDA2P-ACD's TRM apparently states that is only
supported in the SATA and USB subsystems but not in the Display subsystem.

Thanks in advance.

Regards,

Alexander

0 kcastille over 5 years ago in reply to Alexander Quinones

TI__Guru 56317 points

Alex,

It is supported. The appnote overrides the TRM in this particular case.

Regards,

Kyle

0 Alexander Quinones over 5 years ago in reply to kcastille

Intellectual 310 points

Hi Kyle

thanks for the supplied information.

We will give it a try!

Regards,

Alexander

0 Alexander Quinones over 5 years ago in reply to Alexander Quinones

Intellectual 310 points

Hi Kyle

I followed the instructions of the App Note but when I try to write the CONF1 & 2 registers I see that the expected values somehow are not being taken (see memory browser panel).

I tried that code snippet at the top and at the botton of SBL's initialization routine, without noting any difference.

Am I missing something?

Regards,

Alexander

0 Alexander Quinones over 5 years ago in reply to Alexander Quinones

Intellectual 310 points

actually the check for the SSC_EN_ACK and PLL_LOCK flags is wrong, but it does not matter. The issue here is that that writing to DPLL_VIDEO1_L3_MAIN_PLL_SSC_CONFIGURATION1 and DPLL_VIDEO1_L3_MAIN_PLL_SSC_CONFIGURATION2 somehow fails.

0 kcastille over 5 years ago in reply to Alexander Quinones

TI__Guru 56317 points

Alexander,

There may be some software dependent firewall or MMU setup that may cause issues with writes to specific addresses.

Those registers are mapped at two locations - one is the L3_MAIN and the other is L4_CFG. Can you try the L4_CFG mapping of the register?

1067.skitch.pdf

Regards,

Kyle

0 Alexander Quinones over 5 years ago in reply to kcastille

Intellectual 310 points

Hi Kyle,

great, that helped and now I am able to set the registers correctly (apart that I was setting the wrong values in the corresponding registers).

However, according to the App Note, we should check whether the SCC was correctly enabled by checking the SSC_EN_ACK and PLL_LOCK bits values in the PLL_STATUS register, but they aren't changing at all.

Is the check that I am doing right? or should be something else done before verifing those bits?

Regards,

Alexander

0 Alexander Quinones over 5 years ago in reply to Alexander Quinones

Intellectual 310 points

Hi Kyle,

even the issue mentioned above, we decided to give it a try.

Unfortunately those changes seem to drive crazy the PCLK (Vout_1). The Vout_1 changes between 20 MHz, 100Mhz and 120Mhz somehow:

definitely we are missing something.

Maybe the configuration of the SSC should be done before or after doing anything special?

As you may see above, I am doing that in the SBL, just before loading the App Image.

In the Application we setup all the display settings (i.e. PCLk speed to 120 MHz) but I am sure that we don't override the SCC CONFIG registers...

Thanks in advance.

Regards,

Alexander

0 kcastille over 5 years ago in reply to Alexander Quinones

TI__Guru 56317 points

Alex,

The lines of code you show seem to be writing to the PLL_CONFIGURATION1 and PLL_CONFIGURATION2, rather than PLL_SSC_CONFIGURATION1 and PLL_SSC_CONFIGURATION2. (Though I see in the memory window that the SSC regs are being modified.)

The memory window for PLL_CONFIGURATION1 seems to not be written. Is it?

Can you share your full init sequence code/snippet in a text file?

Regards,

Kyle

0 Alexander Quinones over 5 years ago in reply to kcastille

Intellectual 310 points

sbl_tda2xx_main.zip

Hi Kyle

thanks for your reply.

Attached you may find the original and the modified file with my changes.

As you noted, the Memory View shows that the corresponding registers are changed correctly.

Regards,

Alexander

0 Alexander Quinones over 5 years ago in reply to Alexander Quinones

Intellectual 310 points

ohh, I see your point.

I just missed the _SCC_ in my defines. Still the addresses are valid.

I will give it a try again, just in case some defines where conflicting (though I think in that case the compiler would complaint).

Regards,

Alexander

0 Alexander Quinones over 5 years ago in reply to Alexander Quinones

Intellectual 310 points

Hi Kyle,

i just added the _SCC_ to the defines and test it again and I got the same behavior as before. The clock starts to jump switching frequencies.

Any new advice will be welcome!

Regards,

Alexander

0 kcastille over 5 years ago in reply to Alexander Quinones

TI__Guru 56317 points

Alexander,

I don't think the compiler would complain if two defines point to the same address.

Can you comment on the memory view for the PLL_CONFIGURATION1 register? This reg should not be 0x0.

Regards,

Kyle

0 Alexander Quinones over 5 years ago in reply to kcastille

Intellectual 310 points

Hi Kyle

I was busy working on other issue but now i am back to this topic.

Why is PLL_CONFIGURATION1 zero? well, because that code is done in the SBL, where those clock settings are still not set.

In the App Note is not clear if there are preconditions to fulfill before setting PLL_SSC_CONFIGURATION1 nad PLL_SSC_CONFIGURATION2.

So, in the meantime I moved the code to set those registers in our display driver in the application, where all the DPLL for the DSS is done, just after setting the multiplier and dividers:

But basically the same issue happens, that is, the PCLK gets corrupted.

Should the setup of the SCC be done in a specific location in the DPLL's DSS initialization sequence?

Regards,

Alexander

0 Kevin Lavery over 5 years ago in reply to Alexander Quinones

TI__Mastermind 21640 points

Alexander,

As an idea from looking at your code, have you tried writing HDMI_PLL_SSC_CONFIGURATION2 before HDMI_PLL_SSC_CONFIGURATION1? I might also read CONFIG2 to make sure that the write completes before enabling the SSC by writing CONFIG1. (Basically, the way the code is setup now, you are enabling the modulation before configuring it. I'm not sure that changing the order will fix your problem, but I do think it will remove one potential problem.)

Kevin Lavery